ADP5020ACPZ-R7 datasheet(21/28 Pages) AD

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ADP5020

Rev. 0 | Page 21 of 2

APPLICATIONS INFORMATION

POWER GOOD STATUS

The ADP5020 constantly monitors the operating conditions.

When a regulator is activated, it checks if the output voltage

level is above 80% (the power good threshold) of the nominal

level for that output. If the output voltage does not reach the

power good threshold, one of the three power good status bits in

the REG_CONTROL_STATUS register (Address 0x03) is cleared.

If the output voltage reaches the power good threshold, one of

the power good status bits in the REG_CONTROL_STATUS

contains the following three power good bits: BK1_PGOOD for

the Buck 1 output (Bit 3), BK2_PGOOD for the Buck 2 output

(Bit 2), and LDO_PGOOD for the LDO output (Bit 1).

XSHTDN LOGIC

In addition to the power good information for each enabled

regulator, an XSHTDN signal is generated, as shown in Table 18. If

one or more regulators are unused in a specific application, the

masking bits for the disabled regulator, which are fuse pro-

grammable and I2C programmable after device startup, must be

set to 1 to mask the status of the power good signal. Besides having

the masking bits predefined through factory-programmed fuses

(necessary only for operation with the EN signal), the ADP5020

provides three masking bits that are accessible through the I2C

interface. These bits are located in the OPERATIONAL_

CONTROL register (Address 0x04), where the BK1_XSHTDN

bit (Bit 3) is the mask (if set to 1) for Buck 1, the BK2_XSHTDN bit

(Bit 2) is the mask (if set to 1) for Buck 2, and the LDO_

XSHTDN bit (Bit 3) is the mask (if set to 1) for the LDO. Addi-

tional failures that are verified are the input (VDDA) undervoltage

condition, as described in the Undervoltage Lockout section; and

an overtemperature condition of the die, as described in the

Thermal Shutdown section. As soon as one of these conditions

occurs, the active regulators are immediately turned off, and the

XSHTDN pin is set to 0.

COMPONENTS SELECTION

Buck Inductor

The buck inductor is chosen to meet output ripple current and

ripple voltage requirements with minimum size. The fast load

transient response and wide frequency bandwidth are also impor-

tant factors for inductor selection. The minimum inductance of the

buck converter is derived from the following equation:

OUT

INMAX

OUT

INMAX

MINBUCK

−

)

(

(1)

where:

VINMAX is the maximum input supply voltage.

VOUT is the regulator output voltage in the buck converter.

fSW is the converter switching frequency.

r is the inductor ripple factor, which is selected as 30%.

Peak inductor current is calculated in the following equation:

ILMAX = IOUT + 0.5 × r × IOUT

(2)

The calculated minimum Buck 2 inductor value is 2.2 μH. The

maximum peak inductor current is 325 mA. A ceramic inductor

such as the Taiyo Yuden BRL2012T2R2M, with a 600 mA satu-

ration current in a 2 mm × 1.2 mm × 1 mm package, can be used.

For the Buck 1 converter, the calculated minimum inductance is

2.2 μH, with maximum peak current of 690 mA. A ceramic

inductor such as the Taiyo Yuden BRL2518T2R2M, with a 1 A

saturation current in a 2.5 mm × 1.8 mm × 1.2 mm package, is

recommended.

Input Capacitor Selection

The input capacitors are used to decouple the parasitic inductance

of input wires to the converters and to reduce the input ripple

voltage and the switching ac current flow to the battery rail. The

capacitors are selected to support the maximum input operating

voltage and the maximum rms current. The capacitance must also

be large enough to ensure input stability and suppress input ripple.

ESR should as small as possible to decouple the noise. MLCC

ceramic capacitors are a good choice for battery-powered appli-

cations because of their high capacitance, small size, and low ESR.

A 10 μF ceramic capacitor (for example, the JMK107BJ106MA-T

from Taiyo Yuden) is recommended.

Output Capacitor Selection

Output capacitor selection should be based on the following three

factors:

•

Maximizing the control loop bandwidth of the converter

with the LC filter

•

Minimizing the output voltage ripple

•

Minimizing the size of the capacitor

Note that the output ripple is the combination of several factors,

including the inductor ripple current (ΔIL), the ESR and ESL

output capacitors, and the capacitor impedance at the switching

frequency.

In buck converters, the output ripple can be calculated as

follows:

ΔVOUTRIPPLE = ΔIL

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

OUT

ESL

ESR

ΔIL = r × IOUT

Capacitor manufacturer data sheets show the ESR and ESL

value. In real-life applications, the ripple voltage may be higher

because the equations provided in this data sheet do not consider

parameters such as board/package parasitic inductance and

capacitance. The minimum recommended capacitance is no less

than 4.0 μF for Buck 1, 2.0 μF for Buck 2, and 0.4 μF for the

LDO.

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