ADP5020ACPZ-R7 datasheet(7/28 Pages) AD

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ADP5020

Rev. 0 | Page 7 of

I2C TIMING SPECIFICATIONS

Table 6.

Parameter

Min

Max

Unit

Description

fSCL

400

kHz

SCL clock frequency

tHIGH

0.6

μs

SCL high time

tLOW

1.3

μs

SCL low time

tSU,DAT

100

Data setup time

tHD,DAT1

0.9

μs

Data hold time

tSU,STA

0.6

μs

Setup time for repeated start

tHD,STA

0.6

μs

Hold time for start/repeated start

tBUF

1.3

μs

Bus free time between a stop condition and a start condition

tSU,STO

0.6

μs

Setup time for stop condition

tRISE

20 + 0.1CB

300

Rise time of SCL/SDA

tFALL

20 + 0.1CB

300

Fall time of SCL/SDA

tSP

Pulse width of suppressed spike

CB2

400

Capacitive load for each bus line

1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the SCL falling edge.

2 CB is the total capacitance of one bus line in picofarads (pF).

Timing Diagram

SDA

SCL

S = START CONDITION

Sr = START REPEATED CONDITION

P = STOP CONDITION

tLOW

tRISE

tSU,DAT

tHD,DAT

tHIGH

tFALL

tSU,STA

tHD,STA

tSP tRISE

tSU,STO

tBUF

Figure 3. I2C Interface Timing Diagram

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