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ADP5020ACPZ-R7 数据表(PDF) 19 Page - Analog Devices |
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ADP5020ACPZ-R7 数据表(HTML) 19 Page - Analog Devices |
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19 / 28 page ![]() ADP5020 Rev. 0 | Page 19 of 28 POWER-ON SEQUENCE USING THE I2C INTERFACE When the EN pin is low, the regulator sequence is controlled by the application processor sending I2C commands to control the activation. When Bit 4 (EN_ALL) in the REG_CONTROL_ STATUS register (Address 0x03) is set to 1, the regulator sequence is as follows: 1. Buck 1 2. LDO 3. Buck 2 This sequence can be factory programmed through fuses. Unused regulators can also be fuse programmed to be turned off during sequencing. tREG1 <50µs tREG2 tREG3 tXSHTDN VDDx VUVLOR VUVLOF POR INTERNAL POR EN BUCK 1 BUCK 2 LDO XSHTDN I2C BUS I2C SET/CLEAR xxx_XSHTDN BITS Figure 25. Activation and Power Failure Conditions EN BK1_EN = 1 BK2_EN = 1 FORCE_XS = 1 FORCE_XS = 0 BK1_EN, LDO_EN, BK2_EN = 0 LD0_EN = 1 I2C BUS BUCK 1 BUCK 2 XSHTDN LDO Figure 26. Individual Activation Through I2C Commands |
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