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ADP5020

Rev. 0 | Page 17 of

POWER-UP/POWER-DOWN SEQUENCE

SEQUENCER

The sequencer is enabled after a low-to-high transition of the

enable pin (EN). When EN is low or programmed as an output, the

sequencing is controlled and timed by the application processor

via the I2C commands.

Each regulator inside the ADP5020 is controlled by the

sequencer block. The sequencer is factory programmed with

a default turn-on sequence that determines the activation order of

the regulators. The default activation order is listed as follows:

Buck 1

LDO

Buck 2

A low-to-high transition of the EN pin, when programmed

as an input, or an I2C command setting Bit 4 (EN_ALL) in the

REG_CONTROL_STATUS register (Address 0x03), starts the

sequencer.

The activation delay for the first regulator is determined by the

turn-on delay of the band gap, oscillator, and other internal

circuits. Therefore, the first regulator cannot be activated before

a typical 5 ms delay time has elapsed. Delays between the first

and second regulator and from the second to third regulator are

hard coded to a specific time (tREG1, tREG2, and tREG3). The delay

time starts from the moment a regulator has reached the power

good threshold (see Figure 22).

DEFAULT POWER-ON SEQUENCE WITH EN PIN

Figure 22 shows the default regulator sequencing after a low-to-

high transition of the EN pin. The regulator order is factory

programmed and can be changed for specific applications. The

power good signal (POK) turns to high if the regulator voltage

is ≥80% of the target voltage. The second regulator checks the

POK signal of the first regulator and waits the preset delay time

(tREG2) before turning on. In addition to changing the regulator

order, it is also possible to disable the unused regulator. Additional

fuses allow disabling of the association between XSHTDN genera-

tion and the POK signal for a specific regulator. The power good

signal of an unused regulator must be masked, via dedicated fuse

and user registers, to prevent the XSHTDN output from being

forced low. A host processor controller, connected to the I2C bus,

can override the masking fuses by accessing the following bits in

the OPERATIONAL_CONTROL register (Address 0x04): Bit 3

(BK1_XSHTDN, for Buck 1), Bit 2 (BK2_XSHTDN, for Buck 2),

and Bit 3 (LDO_XSHTDN, for LDO). Writing 0 to these register

bits requires that power good be true to release the XSHTDN pin

to high. Writing 1 to these bits causes the regu-lator state to be

ignored, and XSHTDN must depend on the active and

unmasked regulators.

The regulators can also be activated individually via the I2C

commands. The host specifies which regulator is to be turned

on or off by setting or clearing the following selection bits in the

REG_CONTROL_STATUS register (Address 0x03): Bit 7

(BK1_EN), Bit 6 (BK2_EN), or Bit 5 (LDO_EN). When the

regulators are individually activated by I2C commands, the auto

sequencing is disabled and the host controls the turn-on and

turn-off timing (see Figure 26).

BUCK 1

LDO

BUCK 2

XSHTDN

tREG1

tREG2

POK

tREG3

tXSHTDN

Figure 22. Automatic Sequencing with EN Low-to-High Transition

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