ADP5020ACPZ-R7 datasheet(20/28 Pages) AD

20 / 28 page

ADP5020

Rev. 0 | Page 20 of 2

The application processor, together with the regulator power

good signal, controls the XSHTDN pin, as shown in Table 18.

After a regulator is enabled and no failure condition is detected

(power good = 1 in Bits[3:1] of the REG_CONTROL_STATUS

trolled by Bit 0 (FORCE_XS) in the REG_CONTROL_STATUS

EN signal is high, the level on the XSHTDN pin depends on the

power good condition of the regulator.

Table 18. Truth Table

I2C Regulator Enable

Power

Good

FORCE_XS

XSHTDN

1 X = don’t care.

POWER-UP/POWER-DOWN STATE FLOW

When the device is enabled, the UVLO circuit constantly monitors

the supply voltage. If the supply voltage falls below the VUVLOF

threshold, typically 2.0 V, the regulators are immediately turned

off. All the internal analog circuits are then disabled to save power,

except the power-on reset (POR) circuit, which detects if the supply

voltage is dropping. If the supply voltage is higher than the POR

threshold, the POR circuit keeps the logic circuits operating

properly and retains the internal values of the registers. This

POR threshold is set to approximately 1.4 V.

If the supply voltage goes below the VUVLOR threshold, but not

below the POR threshold, the registers are preserved. If the supply

voltage returns to the normal operating level (above VUVLOR),

a new activation does not require initialization of the registers.

However, if the supply voltage goes below the POR level, the

device is held in reset state. When the input voltage resumes the

proper operating level, the host controller must reload the registers.

The additional current required to keep the POR monitoring

circuits alive during UVLO is estimated to be approximately 1 μA.

NO POWER

VDDx < VPOR

EN = LOW AND 12C OFF

COMMAND

OR VDDx < VUVLOF

I2C

COMMANDS

INTERNAL

RESET

EN = HIGH

STAND BY

TSD

STARTUP

SEQUENCER

NORMAL

OPERATION

SEQUENCE

END, AND ALL REGULATIONS ARE

POWER GOOD

VDDx > VPOR

LEVEL

EN = LOW

EN = LOW OR I2C OFF

COMMAND

OR VDDx < VUVLOF

DEVICE ENABLED

(EN_ALL OR EN = HIGH)

Figure 27. State Flow

ADP5020ACPZ-R7 数据表(PDF) 20 Page - Analog Devices

ADP5020ACPZ-R7 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载