AT89LP428 datasheet(22/149 Pages) ATMEL

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3654A–MICRO–8/09

AT89LP428/828

6.3

Internal RC Oscillator

The AT89LP428/828 has an Internal RC oscillator (IRC) tuned to 8.0 MHz ±1.0% at 5.0V and

25°C. When enabled as the clock source, XTAL1 and XTAL2 may be used as P4.0 and P4.1,

respectively. XTAL2 may also be configured to output a divided version of the system clock. The

frequency of the oscillator may be adjusted within limits by changing the RC Calibration Byte

stored at byte 64 of the User Signature Array. This location may be updated using the IAP inter-

face (location 00C0H in SIG space) or by an external device programmer (UROW location

0040H). See “User Signature and Analog Configuration” on page 122.

6.4

System Clock Out

When the AT89LP428/828 is configured to use either an external clock or the internal RC oscil-

lator, the system clock divided by 2 may be output on XTAL2 (P4.1). The clock out feature is

enabled by setting the COE bit in CLKREG. For example, setting COE = “1” when using the

internal oscillator will result in a 4.0 MHz clock output on P4.1. P4.1 must be configured as an

output in order to use the clock out feature.

6.5

System Clock Divider

The CDV

2-0 bits in CLKREG allow the system clock to be divided down from the selected clock

source by powers of 2. The clock divider provides users with a greater frequency range when

using the Internal RC Oscillator. For example, to achieve a 1 MHz system frequency when using

the IRC, CDV

2-0 should be set to 011B for divide-by-8 operation. The divider can also be used to

reduce power consumption by decreasing the operational frequency during non-critical periods.

The resulting system frequency is given by the following equation:

where f

OSC is the frequency of the selected clock source. The clock divider will prescale the clock

for the CPU and all peripherals. The value of CDV may be changed at any time without interrupt-

ing normal execution. Changes to CDV are synchronized such that the system clock will not

pass through intermediate frequencies. When CDV is updated, the new frequency will take

affect within a maximum period of 32 x t

OSC.

SYS

OSC

CDV

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