AT89LP428 datasheet(35/149 Pages) ATMEL

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3654A–MICRO–8/09

AT89LP428/828

10. I/O Ports

The AT89LP428/828 can be configured for between 23 and 30 I/O pins. The exact number of

I/O pins available depends on the package type and the clock and reset options as shown in

Table 10-1.

10.1

Port Configuration

All port pins on the AT89LP428/828 may be configured to one of four modes: quasi-bidirectional

(standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may

be assigned in software on a pin-by-pin basis as shown in Table 10-2 using the registers listed in

Table 10-3. The Tristate-Port User Fuse determines the default state of the port pins. When the

fuse is enabled, all port pins default to input-only mode after reset. When the fuse is disabled, all

port pins, with the exception of the analog inputs, P2.4, P2.5, P2.6 and P2.7, default to quasi-

bidirectional mode after reset and are weakly pulled high. The analog input pins always reset to

input-only (tristate) mode. Each port pin also has a Schmitt-triggered input for improved input

noise rejection. During Power-down all the Schmitt-triggered inputs are disabled with the excep-

tion of P3.2 (INT0), P3.3 (INT1), P3.6 (RST), P4.0 (XTAL1) and P4.1 (XTAL2) which may be

used to wake up the device. Therefore, P3.2, P3.3, P3.6, P4.0 and P4.1 should not be left float-

ing during Power-down. In addition any pin of Port 1 configured as a GPI input will also remain

active during Power-down to wake-up the device. These interrupt pins should either be disabled

before entering Power-down or they should not be left floating.

Table 10-1.

I/O Pin Configurations

Clock Source

Reset Option

Package

Number of I/O Pins

External Crystal or

Resonator

External RST Pin

PDIP

TQFP or PLCC

No external reset

PDIP

TQFP or PLCC

External Clock

External RST Pin

PDIP

TQFP or PLCC

No external reset

PDIP

TQFP or PLCC

Internal RC Oscillator

External RST Pin

PDIP

TQFP or PLCC

No external reset

PDIP

TQFP or PLCC

Table 10-2.

Configuration Modes for Port x, Bit y

PxM0.y

PxM1.y

Port Mode

Quasi-bidirectional

Push-pull Output

Input Only (High Impedance)

Open-drain Output

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