AT89LP428 datasheet(36/149 Pages) ATMEL

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3654A–MICRO–8/09

AT89LP428/828

10.1.1

Quasi-bidirectional Output

Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi-

bidirectional port can be used both as an input and output without the need to reconfigure the

port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an

external device to pull the pin low. When the pin is driven low, it is driven strongly and able to

sink a large current. There are three pull-up transistors in the quasi-bidirectional output that

serve different purposes.

One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port latch for the

pin contains a logic “1”. This very weak pull-up sources a very small current that will pull the pin

high if it is left floating.

A second pull-up, called the “weak” pull-up, is turned on when the port latch for the pin contains

a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source

current for a quasi-bidirectional pin that is outputting a “1”. If this pin is pulled low by an external

device, this weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the

pin low under these conditions, the external device has to sink enough current to overpower the

weak pull-up and pull the port pin below its input threshold voltage.

The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-

high transitions on a quasi-bidirectional port pin when the port latch changes from a logic “0” to a

logic “1”. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the

port pin high. The quasi-bidirectional port configuration is shown in Figure 10-1.

Figure 10-1. Quasi-bidirectional Output

Table 10-3.

Port Configuration Registers

Port

Port Data

Port Configuration

P1 (90H)

P1M0 (C2H), P1M1 (C3H)

P2 (A0H)

P2M0 (C4H), P2M1 (C5H)

P3 (B0H)

P3M0 (C6H), P3M1 (C7H)

P4 (C0H)

P4M0 (BEH), P4M1 (BFH)

1 Clock Delay

(D Flip-Flop)

Strong

Very

Weak

Port

VCC

From Port

Input

Data

PWD

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