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AT89LP428 数据表(PDF) 41 Page - ATMEL Corporation |
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AT89LP428 数据表(HTML) 41 Page - ATMEL Corporation |
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41 / 149 page ![]() 41 3654A–MICRO–8/09 AT89LP428/828 11. Enhanced Timer 0 and Timer 1 with PWM The AT89LP428/828 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following features: • Two 16-bit timer/counters with 16-bit reload registers • Two independent 8-bit precision PWM outputs with 8-bit prescalers •UART or SPI baud rate generation using Timer 1 •Output pin toggle on timer overflow • Split timer mode allows for three separate timers (two 8-bit, one 16-bit) •Gated modes allow timers to run/halt based on an external input Timer 0 and Timer 1 have similar modes of operation. As timers, they increase every clock cycle by default. Thus, the registers count clock cycles. Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency. The timer rate can be prescaled by a value between 1 and 16 using the Timer Prescaler (see Table 6-2 on page 23). Both Timers share the same prescaler. As counters, the timer registers are incremented in response to a 1-to-0 transition at the corre- sponding input pins, T0 or T1. The external input is sampled every clock cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since 2 clock cycles are required to recognize a 1-to-0 transition, the maximum count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle of the input sig- nal, but it should be held for at least one full clock cycle to ensure that a given level is sampled at least once before it changes. Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes: variable width timer, 16-bit auto-reload timer, 8-bit auto-reload timer, and split timer. The control bits C/T in the Special Function Register TMOD select the Timer or Counter function. The bit pairs (M1, M0) in TMOD select the operating modes. Table 11-1. Timer 0/1 Register Summary Name Address Purpose Bit-Addressable TCON 88H Control Y TMOD 89H Mode N TL0 8AH Timer 0 low-byte N TL1 8BH Timer 1 low-byte N TH0 8CH Timer 0 high-byte N TH1 8DH Timer 1 high-byte N TCONB 91H Mode N RL0 92H Timer 0 reload low-byte N RL1 93H Timer 1 reload low-byte N RH0 94H Timer 0 reload high-byte N RH1 95H Timer 1 reload high-byte N |
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