ATmega169PV-8MCH datasheet(23/393 Pages) ATMEL

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8018N–AVR–08/09

ATmega169P

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,

the CPU is halted for two cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 7-1 lists the typical pro-

gramming time for EEPROM access from the CPU.

The following code examples show one assembly and one C function for writing to the

EEPROM. To avoid that interrupts will occur during execution of these functions, the examples

assume that interrupts are controlled (e.g. by disabling interrupts globally). The examples also

assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

Table 7-1.

EEPROM Programming Time

Symbol

Number of Calibrated

RC Oscillator Cycles

Typical Programming Time

EEPROM write (from CPU)

27 072

3.3 ms

ATmega169PV-8MCH 数据表(PDF) 23 Page - ATMEL Corporation