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ATmega169PV-8MCH 数据表(PDF) 29 Page - ATMEL Corporation |
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ATmega169PV-8MCH 数据表(HTML) 29 Page - ATMEL Corporation |
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29 / 393 page  29 8018N–AVR–08/09 ATmega169P 7.5 I/O Memory The I/O space definition of the ATmega169P is shown in ”Register Summary” on page 371. All ATmega169P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega169P is a com- plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with reg- isters 0x00 to 0x1F only. The I/O and peripherals control registers are explained in later sections. 7.6 General Purpose I/O Registers The ATmega169P contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Sta- tus Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit- accessible using the SBI, CBI, SBIS, and SBIC instructions. 7.6.1 GPIOR2 – General Purpose I/O Register 2 7.6.2 GPIOR1 – General Purpose I/O Register 1 7.6.3 GPIOR0 – General Purpose I/O Register 0 Bit 765 4321 0 0x2B (0x4B) MSB LSB GPIOR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 0000 0 Bit 765 4321 0 0x2A (0x4A) MSB LSB GPIOR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 0000 0 Bit 765 4321 0 0x1E (0x3E) MSB LSB GPIOR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 0000 0 |
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