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ATmega169PV-8MCH 数据表(PDF) 27 Page - ATMEL Corporation |
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ATmega169PV-8MCH 数据表(HTML) 27 Page - ATMEL Corporation |
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27 / 393 page  27 8018N–AVR–08/09 ATmega169P 7.4 EEPROM Register Description 7.4.1 EEARH and EEARL – EEPROM Address Register • Bits 15:9 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 8:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 7.4.2 EEDR – EEPROM Data Register • Bits 7:0 – EEDR7:0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 7.4.3 EECR – EEPROM Control Register • Bits 7..4 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter- rupt when EEWE is cleared. • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at Bit 151413 121110 9 8 0x22 (0x42) ––– ––– – EEAR8 EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 765 432 10 Read/Write RR RRR RR R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 X X XXX XXX X Bit 765 432 10 0x20 (0x40) MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 43 2 1 0 0x1F (0x3F) – – – – EERIE EEMWE EEWE EERE EECR Read/Write RRRR R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0 |
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