ATmega16HVB datasheet(111/273 Pages) ATMEL

111 / 273 page

111

8042A–AVR–07/09

ATmega16HVB/32HVB

19.6

Configuration and Usage

While the CC-ADC is converting, the CPU can enter sleep mode and wait for an interrupt. After

adding the conversion data for the Coulomb Counting, the CPU can go back to sleep again. This

reduces the CPU workload, and allows more time spent in low power modes, reducing power

consumption.

To use the CC-ADC the bandgap voltage reference must be enabled separately, see ”Voltage

Reference and Temperature Sensor” on page 123.

The CC-ADC will not consume power when CADEN is cleared. It is therefore recommended to

switch off the CC-ADC whenever the Coulomb Counter or Regular Current Detection functions

are not used. The CC-ADC is automatically disabled in Power-off mode.

After the CC-ADC is enabled by setting the CADEN bit, the first four conversions do not contain

useful data and should be ignored. This also applies after clearing the CADSE bit, or after

changing the CADPOL or CADVSE bits.

The conversion times and sampling intervals are controlled by the Ultra Low Power RC Oscilla-

tor (see ”Ultra Low Power RC Oscillator” on page 27), and will depend on its actual frequency.

To obtain accurate coulomb counting results, the actual conversion time should be calculated.

Refer to ”System Clock and Clock Options” on page 25 for details.

19.7

19.7.1

CADCSRA – CC-ADC Control and Status Register A

• Bit 7 – CADEN: CC-ADC Enable

When the CADEN bit is cleared (zero), the CC-ADC is disabled, and any ongoing conversions

will be terminated. When the CADEN bit is set (one), the CC-ADC will continuously measure the

voltage drop over the external sense resistor R

SENSE. In Power-off, the CC-ADC is always

disabled.

Note that the bandgap voltage reference must be enabled separately, see ”Voltage Reference

and Temperature Sensor” on page 123.

• Bit 6 – CADPOL: CC-ADC Polarity

The CADPOL bit is used to change input sampling polarity in the Sigma Delta Modulator. Writing

this bit to one, the polaritiy will be negative. When the bit is zero, the polarity will be positive.

• Bit 5 - CADUB: CC-ADC Update Busy

The CC-ADC operates in a different clock domain than the CPU. Whenever a new value is writ-

ten to CADCSRA, CADCSRC, CADRCC or CADRDC, this value must be synchronized to the

CC-ADC clock domain. Subsequent writes to these registers will be blocked during this synchro-

nization. Synchronization of one of the registers will block updating of all the others. The CADUB

bit will be read as one while any of these registers is being synchronized, and will be read as

zero when neither register is being synchronized.

Bit

432

(0xE6)

CADEN

CADPOL

CADUB

CADAS1

CADAS0

CADSI1

CADSI0

CADSE

CADCSRA

Read/Write

R/W

Initial Value

ATmega16HVB 数据表(PDF) 111 Page - ATMEL Corporation

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