ATmega16HVB datasheet(113/273 Pages) ATMEL

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113

8042A–AVR–07/09

ATmega16HVB/32HVB

• Bit 5 – CADRCIE: CC-ADC Regular Current Interrupt Enable

When the CADRCIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC

Regular Current Interrupt is enabled.

• Bit 4 – CADICIE: CC-ADC Instantaneous Current Interrupt Enable

When the CADICIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC

Instantaneous Current Interrupt is enabled.

• Bit 2 – CADACIF: CC-ADC Accumulate Current Interrupt Flag

The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-

ADC Accumulate Current Interrupt is executed if the CADACIE bit and the I-bit in SREG are set

(one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling

Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag.

• Bit 1 – CADRCIF: CC-ADC Regular Current Interrupt Flag

The CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conver-

sion is greater than, or equal to, the compare values set by the CC-ADC Regular

Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge

Current Level, and a negative value is compared to the Regular Discharge Current Level. The

CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set

(one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling

Vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.

• Bit 0 – CADICIF: CC-ADC Instantaneous Current Interrupt Flag

The CADICIF bit is set (one) when a CC-ADC Instantaneous Current conversion is completed.

The CC-ADC Instantaneous Current Interrupt is executed if the CADICIE bit and the I-bit in

SREG are set (one). CADICIF is cleared by hardware when executing the corresponding Inter-

rupt Handling vector. Alternatively, CADICIF is cleared by writing a logic one to the flag.

19.7.3

CADCSRC – CC-ADC Control and Status Register C

• Bit 7:1 – Res: Reserved

These bits are reserved bits and will always read as zero.

• Bit 0 – CADVSE: CC-ADC Voltage Scaling Enable

Setting this bit enables the internal Voltage Scaling. When enabling the internal Voltage Scaling

the internal CC-ADC reference will be divided by 2, affecting the Input Voltage Range and the

resulting step-size. Table 19-3 shows the Input Voltage Range and the conversion value step-

size for the CADVSE settings.

Bit

(0xE8)

–

CADVSE

CADCSRC

Read/Write

R/W

Initial Value

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