ADM1029ARQZ-R7 datasheet(47/50 Pages) ONSEMI

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ADM1029

AIN REGISTERS

Bit

Name

R/W

Description

GPIO 0 = 1

R/W

Indicates that GPIO0 is being used. Set to 1 on power-up, but can be over-

written by software. Setting this bit to 0 means AIN0 is being used.

GPIO 1 = 1

R/W

Indicates that GPIO1 is being used. Set to 1 on Power-up, but can be over-

written by software. Setting this bit to 0 means AIN1 is being used.

GPIO 2 = 1

R/W

Indicates that GPIO2 is being used. Set to 1 on power-up, but can be over-

written by software.

GPIO 3 = ?

R/W

Indicates that GPIO3 is being used. Setting this bit to 0 means TDM1 is being

used. The ADM1029 can detect on power-up if TDM1 is connected. If so,

this bit is set to 0; otherwise it is set to 1. The default setting can be overwrit-

ten by software.

GPIO 4 = ?

R/W

Indicates that GPIO4 is being used. Setting this bit to 0 means TDM1 is being

used. The ADM1029 can detect on power-up if TDM1 is connected. If so,

this bit is set to 0; otherwise it is set to 1. The default setting can be overwrit-

ten by software.

GPIO 5 = ?

R/W

Indicates that GPIO5 is being used. Setting this bit to 0 means TDM2 is being

used. The ADM1029 can detect on power-up if TDM2 is connected. If so,

this bit is set to 0; otherwise it is set to 1. The default setting can be overwrit-

ten by software.

GPIO 6 = ?

R/W

Indicates that GPIO6 is being used. Setting this bit to 0 means TDM2 is being

used. The ADM1029 can detect on power-up if TDM2 is connected. If so,

this bit is set to 0; otherwise it is set to 1. The default setting can be overwrit-

ten by software.

Reserved

Unused. Will read back 0.

NOTE

Question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up.

* Behavior (Power-On Default 00h)

Bit

Name

R/W

Description

Assert CFAULT on

R/W

When this bit is set, CFAULT is asserted when AINx

* exceeds the AINx*

HI_LIM = 0

high limit.

Alarm speed on

R/W

When this bit is set, the fans go to alarm speed when AINx

* exceeds the

HI_LIM = 0

AINx

* high limit.

INT on HI_LIM = 0

R/W

When this bit is set, INT is asserted when AINx

* exceeds the AINx* high limit.

Alarm below low = 0

R/W

This bit indicates whether an alarm (INT, CFAULT or Alarm Speed) is

asserted when AINx

* goes above or below the Low Limit. 1 = above. 0 = below.

Assert CFAULT on

R/W

When this bit is set, CFAULT is asserted when AINx

* crosses the AINx*

LO_LIM = 0

low limit. Bit 3 decides whether CFAULT is asserted for going above or below

the Low Limit.

Alarm speed on

R/W

When this bit is set, the fans go to alarm speed when AINx

* crosses the AINx*

LO_LIM = 0

low limit. Bit 3 decides whether Alarm Speed is asserted for going above or

below the Low Limit.

INT on LO_LIM = 0

R/W

When this bit is set, INT is asserted when AINx

* crosses the AINx* low limit. Bit

3 decides whether INT is asserted for going above or below the Low Limit.

Latch AIN Fault = 0

R/W

This bit latches an out-of-limit event (i.e., when AINx

* goes above the high

limit or crosses the low limit) on the AINx

* channel. This bit is cleared by

writing a 0 to it.

*“x” denotes the number of the AIN channel. Register 50h controls AIN0 and 51h controls AIN1.

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