ADM1029ARQZ-R7 datasheet(16/50 Pages) ONSEMI

16 / 50 page

Rev. 1 | Page 16 of 50 | www.onsemi.com

A fan will only be driven if it is defined as being supported by

the system in register 03h. If Bit 0 of this register is set, it indi-

cates that Fan 1 is installed. This is the power-on default. If

Bit 1 is set, it indicates that Fan 2 is installed. This bit is set by

the state of Pin 18 at power-up. This register is read/write and

the default/power-on setting can be overwritten. If a fan is not

supported in register 03h it will not be driven, even if it is physi-

cally installed.

The PWM outputs are open-drain outputs. They require pull-up

resistors and must be amplified and buffered to drive the fans.

Minimum Speed

The normal operating fan speed is set by the four LSBs of the

Fan 1 and Fan 2 Minimum/Alarm Speed Registers (addresses

60h, 61h). These bits also set the minimum speed at which a fan

will run in automatic control mode. These bits should be set to

05h. This corresponds to 33% PWM duty-cycle, which is the

lowest speed at which most fans will run reliably.

Fan(s) will run at minimum speed if there is no fault condition,

automatic fan speed is disabled, and there are no other over-

riding conditions.

Alarm Speed

Alarm speed is set by the four MSBs of the Fan 1 and Fan 2

Minimum/Alarm Speed Registers (addresses 60h, 61h). Fan(s)

will run at alarm speed if any of the following conditions occurs,

assuming the condition has not been masked out using the Fan

Event Mask Registers:

• Setting Bit 0 of register 07h forces Fan 1 to run at alarm speed

(Set Fan x Alarm Speed Register).

• Setting Bit 1 of register 07h forces Fan 2 to run at alarm speed

(Set Fan x Alarm Speed Register).

If monitoring is disabled by clearing Bit 4 of the Con-

figuration Register, all fans controlled by the ADM1029

will run at alarm speed.

• When a GPIO pin is configured as an input by setting Bit 0 of

the corresponding GPIO Behavior Register, and Bit 4 of the

GPIO Behavior Register is also set, all fans controlled by the

ADM1029 will go to alarm speed when the logic input is

asserted (high or low, depending on the polarity bit, Bit 1 of

the corresponding GPIO Behavior Register).

• If Bit 7 of a Fan Fault Action Register is set (18h—Fan 1, 19h

—Fan 2) the corresponding fan will go to alarm speed when

CFAULT is pulled low by an external source.

• If a tach measurement exceeds the set limit, all fans controlled

by the ADM1029 will run at alarm speed.

• If a fan fault input pin is asserted (low), all fans controlled by

the ADM1029 will run at alarm speed.

• If Bit 1 of a Temp. Fault Action Register is set (40h—Local

Sensor, 41h—Remote 1, 42h—Remote 2), all fans controlled

by the ADM1029 will go to alarm speed if the corresponding

temperature high limit is exceeded.

• If Bit 5 of a Temp. Fault Action Register is set, all fans con-

trolled by the ADM1029 will go to alarm speed if a temperature

input crosses the corresponding temperature low limit, the

direction depending on the setting of Bit 3 of the Temp. Con-

trol register. (0 = alarm when input goes below low limit, 1 =

alarm when input goes above low limit).

• If Bit 1 of an AIN Behavior Register is set (50h—AIN0,

51h—AIN1), all fans controlled by the ADM1029 will go to

alarm speed if the corresponding AIN high limit is exceeded.

• If Bit 5 of an AIN Behavior Register is set, all fans controlled

by the ADM1029 will go to alarm speed if an analog input

crosses the corresponding AIN low limit, the direction depend-

ing on the setting of Bit 3 of the AIN control register. (0 =

alarm when input goes below low limit, 1 = alarm when input

goes above low limit).

• If a thermal override occurs while the ADM1029 is in sleep

mode, all fans controlled by the ADM1029 will run at

alarm speed.

Hot-Plug Speed

Hot-plug speed is set by the four LSBs of the Fan 1 and Fan 2

Configuration Registers (addresses 68h and 69h). The PWM

frequency is set by Bits 4 and 5 of these registers, while Bits 6

and 7 set the number of pulses per revolution for fan speed

measurement.

Fan(s) will run at hot-plug speed if any of the following condi-

tions occur, assuming the condition has not been masked using

the Fan Event Mask Registers:

• If a fan is unplugged, the other fan (if any) controlled by the

ADM1029 will run at hot-plug speed.

• Setting Bit 0 of register 08h forces Fan 1 to run at hot-plug

speed (Set Fan x Hot-Plug Speed).

• Setting Bit 1 of register 08h forces Fan 2 to run at hot-plug

speed (Set Fan x Hot-Plug Speed).

• When a GPIO pin is configured as an input by setting Bit 0 of

the corresponding GPIO Behavior Register, and Bit 5 of the

GPIO Behavior Register is also set, all fans controlled by the

ADM1029 will go to hot-plug speed when the logic input is

asserted (high or low, depending on the polarity bit, Bit 1 of

the corresponding GPIO Behavior Register).

• If Bit 6 of a Fan Fault Action Register is set (18h for Fan 1,

19h for Fan 2) the corresponding fan will go to hot-plug speed

when CFAULT is pulled low by an external source.

Note: If operating conditions and register settings are such that

both alarm speed and hot-plug speed would be triggered, which

one takes priority is determined by Bit 5 of the Fan 1 and Fan 2

Status Registers (addresses 10h and 11h). If this bit is set, hot-plug

speed takes priority. If it is cleared, alarm speed takes priority.

Full Speed

Fans will run at full speed if the corresponding bits in the Set

Fan x Full Speed Register (address 09h) are set: Bit 0 for Fan 1

and Bit 1 for Fan 2.

Fan Mask Registers

The effect of various conditions on fan speed can be enabled or

disabled by mask registers. In all these registers, setting Bit 0 of

the register enables Fan 1 to go to alarm speed or hot-plug speed if

the corresponding event occurs, while setting Bit 1 enables Fan

2. Clearing these bits masks the effect of the corresponding

event on fan speed.

Registers 20h and 21h are Fan Event Mask Registers. Bits 0 and

1 of register 20h enable (bit set) or mask (bit clear) the effect of

a Fan 1 fault (underspeed or fault input) on Fan 1 and Fan 2

speed. Similarly, Bits 0 and 1 of register 21h enable (bit set)

ADM1029

ADM1029ARQZ-R7 数据表(PDF) 16 Page - ON Semiconductor

ADM1029ARQZ-R7 数据表(HTML) 16 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

数据表下载