ADM1029ARQZ-R7 datasheet(17/50 Pages) ONSEMI

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ADM1029

or mask (bit clear) the effect of a Fan 2 Fault on Fan 1 and

Fan 2 speed.

Registers 38h to 3Eh are GPIO X Event Mask Registers. Bits 0

and 1 of these registers enable or mask the effect of a GPIO

assertion on Fan 1 and Fan 2 speed.

Note: Registers 48h to 4Ah are Temp. Cooling Action Regis-

ters. Bits 0 and 1 of these registers enable or mask the effect of

Local, Remote 1, and Remote 2 temperature faults on Fan 1

and Fan 2 speed. These registers also determine which tempera-

ture channel controls each fan in automatic fan speed control

mode, as described later.

Registers 58h and 59h are AIN Event Mask Registers. Bits 0

and 1 of these registers enable or mask the effect of an AIN out-

of-limit event on Fan 1 and Fan 2 speed.

MODES OF OPERATION

The ADM1029 has three different modes of operation. These

modes determine the behavior of the system.

1. PWM Duty Cycle Select Mode (directly sets fan speed under

software control).

2. Thermal Trip Mode

3. Automatic Fan Speed Control Mode

PWM DUTY CYCLE SELECT MODE

The ADM1029 may be operated under software control by

clearing bits <1:0> of the three Temp Cooling Action Registers

(Reg 0x48, 0x49, 0x4A). Once under Software Control, each

fan speed may be controlled by programming values of PWM

Duty Cycle in to the device. Values of PWM Duty Cycle between

0% to 100% may be written to the four LSBs of the Fan 1 and

Fan 2 Minimum/Alarm Speed Registers (addresses 60h, 61h).

to control the speed of each fan. Table IV shows the relationship

between hex values written to the Minimum/Alarm Speed Reg-

isters and PWM duty cycle obtained.

Table IV. PWM Duty Cycle Select Mode

Hex Value

PWM Duty Cycle

14%

20%

27%

33% Recommended

40%

47%

53%

60%

67%

73%

80%

87%

93%

100% (Default)

It is recommended that the minimum PWM duty cycle be set to

33% (0x05). This has been determined to be the lowest PWM

duty cycle that most fans will run reliably at. Note that the PWM

duty cycle values programmed in to these registers also define

the PWM duty cycle that the fans will turn on at, in Automatic

Fan Speed Control Mode. It is recommended that after power-

up, the PWM duty cycle is set to 33% before enabling Automatic

Fan Speed Control.

THERMAL TRIP MODE

The ADM1029 can thermally trip the fan(s) for simple on/off

fan control, or 2-speed fan control. For example, a fan can be

programmed to run at 33% duty cycle. If the temperature exceeds

the high temperature limit set for that temperature channel, the

fan can automatically trip and run at Alarm Speed. The fan will

continue to run at Alarm Speed even if the temperature error

condition subsides, until the Latch Temp Fault bit (Bit 7 of the

Temp x Fault Action Reg) is cleared in software by writing a 0

to it. To configure Fan 1 normally, run at 33% but to thermally

trip to Alarm Speed for a Remote 2 measured temperature of

70°C, set up the following registers:

1. Configure the normal PWM duty cycle for Fan 1 to 33%.

Fan 1 Minimum/Alarm Speed Reg (0x60) = 0xF5

2. Set the Remote 2 High Temperature Limit = 70°C.

Remote 2 Temp High Limit Reg (0x92) = 0x46

3. Configure Alarm Speed on Overtemperature function for

Remote 2 Temperature channel.

Set Bit 1 of Temp 2 Fault Action Reg (0x42)

4. Enable Fan 1 to be controlled by Remote 2 Temperature.

Set Bit 0 of Temp 2 Cooling Action Reg (0x4A)

Once the fan thermally trips to Alarm Speed, it will continue to

run at Alarm Speed until the temperature drops below the High

Temperature Limit and the Latch Temp Fault bit (Bit 7 of the

Temp 2 Fault Action Reg) is cleared to 0.

EVENT LATCH BITS

Certain events that occur will cause latch bits to be set in vari-

ous registers on the ADM1029. Once a latch bit is set, it will

need to be cleared by software for the system to return to nor-

mal operation. To detect if a latch bit has been set, the INT pin

can be used to signal a latch event to the system supervisor.

Alternatively, the Status Registers can be polled periodically,

and any latch bits that are set can be cleared. The events that

cause latch bits to be set are:

1. Thermal Events. If the fan is run at Alarm Speed on Over-

temperature or Undertemperature, this will set the Latch

Temp Fault bit (Bit 7 of the Temp x Fault Action Registers

0x40–0x42).

2. Missing Fan. If a fan is missing, i.e., has been unplugged, the

Missing Latch bit (Bit 1 of Fan x Status Registers) is set.

3. Hotplugged Fan. If a new fan is inserted into the system, Bit

7 (Hotplug Latch bit) of the Fan x Status Register is set.

4. FAULT Asserted. If the fan becomes stuck and its FAULT

output asserts low, Bit 2 (Fault Latch bit) of the Fan x

Status register is set.

5. TACH Failure. If the fan runs underspeed or becomes stuck,

then Bit 6 (Tach Fault Latch Bit) of the Fan x Status Regis-

ter is set.

*Bits <3:0> set the Minimum PWM duty cycle, bits <7:4> set the Alarm Speed

PWM duty cycle for each fan.

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