E2000 datasheet(28/104 Pages) INTEL

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Electrical Specifications

Datasheet

2.8

Clock Specifications

2.8.1

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor’s core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its

default ratio during manufacturing. Refer to Table 15 for the processor supported

ratios.

The processor uses a differential clocking implementation. For more information on the

processor clocking, contact your Intel field representative. Platforms using a CK505

Clock Synthesizer/Driver should comply with the specifications in Section 2.8.4.

Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications

in Section 2.8.5.

2.8.2

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). Table 16 defines the possible combinations of the signals and the

frequency associated with each combination. The required frequency is determined by

the processor, chipset, and clock synthesizer. All agents must operate at the same

frequency.

The Intel Pentium Dual-Core Desktop processor E2000 series operates at a 800 MHz

FSB frequency (selected by a 200 MHz BCLK[1:0] frequency).

Table 15.

Core Frequency to FSB Multiplier Configuration

Multiplication of System Core

Frequency to FSB Frequency

Core Frequency

(200 MHz BCLK/800 MHz FSB)

Notes1, 2

NOTES:

Individual processors operate only at or below the rated frequency.

Listed frequencies are not necessarily committed production frequencies.

1/6

1.20 GHz

1/7

1.40 GHz

1/8

1.60 GHz

1/9

1.80 GHz

1/10

2 GHz

1/11

2.2 GHz

1/12

2.4 GHz

E2000 数据表(PDF) 28 Page - Intel Corporation

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