STW4811MBRASLASHLF datasheet(55/85 Pages) STMICROELECTRONICS

55 / 85 page

STw4811M/STw4811N

Functional description

CD00131784

55/85

4.5.2

Level shifters

Signal shifting cards voltage level value is automatically done by the multimedia processor

system. Following a card detection, the multimedia processor starts the SD/MMC/SDIO

application by writing in the

configuration 1 register (Table 18) to program LDO VMMC

output supply and then starts the protocol initialization.

The module includes:

●

Five bidirectional level shifter channels compatible with 1.8 V, 1.85 V, 2.6 V, 2.7 V,

2.85 V, 3.0 V, 3.3 V

●

Two unidirectional lines for clock: multimedia processor to card and feedback clock to

multimedia processor for synchronization.

●

Four control signals for channel direction. When direction balls (MCCMDDIR,

MCDATA0DIR, MCDATA2DIR, MCDATA31DIR) are at low level, data is transmitted

from Card to APE. When direction balls are at high level data is transmitted from APE

to card.

When the level shifters are “ON”, the APE interface MCDATA[3:0] and the MCCMD balls

have a 1.5 Mohm pull up resistor to VIO_VMEM.

It is possible to connect another card on the APE interface (1.8 V interface) for this:

●

set to “1” ‘mmc_ls_status’ bits of

configuration 1 register (Table 18) with this

configuration:

–

the APE interface MCDATA[3:0] and the MCCMD balls are put in high impedance

and the pull up resistors are disconnected.

–

the card interface DATAOUT[3:0] and the CMDOUT balls are set to “1” with an

internal 1.5 Mohm pull up resistor

–

the card clock, CLKOUT ball, is set to “0” and the APE feedback clock, MCFBCLK

ball is configured in high impedance.

STW4811MBRA/LF 数据表(PDF) 55 Page - STMicroelectronics

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