STW4811MBRASLASHLF datasheet(40/85 Pages) STMICROELECTRONICS

40 / 85 page

Functional description

STw4811M/STw4811N

40/85

CD00131784

4.3

Power management module

STw4811 includes several regulators that supply the multimedia processor and its

peripherals. All regulators can work in different modes depending on the processor needs.

When the STw4811 is in ‘low current mode’”, the output current is reduced to save energy

via the lower quiescent current. The nominal mode is called high power mode (HPM). The

mode is selected by PWREN ball signal according to both multimedia processor and

STw4811 state.

When PWREN = “0”, sleep mode is selected. HPM is selected as default when PWREN =

“1”.

Except for VIO_VMEM, each supply can be powered down by a bit ‘pdn_(regulator name) or

‘en_(regulator name)’ (

Table 18, 24 and 27). In this mode, the regulator is switched off and

only a leakage current is present (max. 1µA). VCORE, VAUX and VPLL output voltages are

programmable, through main I2C interface, using the ‘(regulator”_sel[x:0])’ bits of the

power

control registers (Table 22 to Table 27).

In addition, an output current limitation prevents high current delivery in case of output short

circuit.

All multimedia processor power supplies have the same soft start to prevent leakage in the

multimedia processor device during the start-up phase. There is an exception with VAUX

which can be started independently.

4.3.1

Bandgap, biasing and references

Figure 10.

Block diagram of biasing and references of the device

All internal

references

VREF_18

All internal

biasing

Bias generator

Voltage reference control

STW4811MBRA/LF 数据表(PDF) 40 Page - STMicroelectronics

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