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STW4811MBRA/LF 数据表(PDF) 74 Page - STMicroelectronics

部件名 STW4811MBRA/LF
功能描述  Power management for multimedia processors
PDF  85 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STW4811MBRA/LF 数据表(HTML) 74 Page - STMicroelectronics

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Electrical and timing characteristics
STw4811M/STw4811N
74/85
CD00131784
LDRT
Transient load
regulation
IOUT = [1; 150] mA
tR = tF = 1 µs
25
mV
tS
Settling time
OFF->ON
IOUT = 0 mA
100
µs
tD
Discharge time
ON>OFF
IOUT = 0 mA
1
ms
Bus line specifications
RA(2)
Pull-up resistor
To prevent bus
from floating
1.5
M
Ω
RB
Pull-down resistor
To prevent bus
from floating
1.5
M
Ω
fDT
Clock frequency
data transfert
mode
With CL = 30pF
52
MHz
fID
Clock frequency
identification mode
With CL = 30pF
400
kHz
TPHC
Propagation time
from Host to card
Figure 15
7ns
TPCH
Propagation time
from card to host
Figure 15
7ns
TSHC
Clock /data skew
time from host to
card
Figure 15
Reference is
CLKOUT
+/- 0.5
ns
TSCH
Clock /data skew
time from card to
host
Figure 15
Reference is
MMCLK
+/- 0.5
ns
TR
Rise time
3
ns
TF
Fall time
3
ns
C1LINE
Between host and
STw4811
Bus line
capacitance
f < 52 MHz
20(3)
pF
C2LINE
Between STw4811
and MMC card
Bus line
capacitance
f < 52 MHz
20 + 20(4)
pF
1.
Guaranteed by design
2.
MMC interface pull up resistors are in EMIF06-HCM01F2 device (7 K
Ω for CMD; 75 KΩ for Data wires)
3.
20 pF for equivalent board parasitic capacitance.
4.
20 pF for EMIF06 protection + 20 pF for board parasitic capacitance.
Table 52.
SD/MMC/SDIO card interface (continued)
Symbol
Description
Test conditions
Min.
Typ.
Max.
Units
VMMC regulator specifications (’pdn_vmmc’ = 1)



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