STW4811MBRASLASHLF datasheet(62/85 Pages) STMICROELECTRONICS

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Electrical and timing characteristics

STw4811M/STw4811N

62/85

CD00131784

VANA

VAUX

Table 42.

LDO regulators - VANA

Symbol

Description

Test conditions

Min.

Typ.

Max.

Units

VANA regulator in high power mode

VBAT

Input power supply Battery voltage

2.7

3.6

4.8

VOUT

Output voltage

-5%

2.5

+5%

IOUT

Output current

ISHORT

Short-circuit

limitation

Quiescent current

IOUT = 0 mA

µA

ILKG

Power-down

current

EN_VANA = 0

µA

PSRR(1)

Guaranteed by design

Power supply

rejection

Vpp = 0.3 V

f < 10 kHz

LIR

Line regulation

VBAT: [2.7; 4.8] V

LDR

Load regulation

IOUT: [0.1; 10] mA

LIRT

Transient line

regulation

ΔVBAT = 300 mV

tR = tF = 10 µs

LDRT

Transient load

regulation

IOUT = [0.1; 10] mA

tR = tF = 1 µs

Table 43.

LDO regulators - VAUX

Symbol

Description

Test conditions

Min.

Typ.

Max.

Units

VAUX regulator in high power mode (pdn_vaux = 1, SLEEP = 0)

VBAT

Input power supply

VOUT = 1.5V

1.7

4.8

VOUT = 1.8/2.5 V

2.7

3.6

4.8

VOUT = 2.8 V

3.6

4.8

VOUT

Output voltage

’vaux_sel’[1:0]

00 (default)

-3%

1.5

1.8

2.5

2.8

+3%

IOUT

Output current

150

ISHORT

Short-circuit

limitation

220

410

Quiescent current

IOUT = 0 mA

µA

STW4811MBRA/LF 数据表(PDF) 62 Page - STMicroelectronics

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