HT68FU50 datasheet(107/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

107

March 15, 2011

¨ TM2AH Register - 16-bit STM

Bit

76543210

Name

D15

D14

D13

D12

D11

D10

R/W

POR

00000000

Bit 7~0

TM2AH: TM2 CCRA High Byte Register bit 7~bit 0

TM2 16-bit CCRA bit 15~bit 8

¨ TM2RP Register - 16-bit STM

Bit

76543210

Name

R/W

POR

00000000

Bit 7~0

TM2RP: TM2 CCRP Register bit 7 ~ bit 0

TM2 CCRP 8-bit register, compared with the TM2 Counter bit 15 ~ bit 8. Comparator P Match

Period

0: 65536 TM2 clocks

1~255: 256 x (1~255) TM2 clocks

These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then

compared with the internal counter's highest eight bits. The result of this comparison can be

selected to clear the internal counter if the T2CCLR bit is set to zero. Setting the T2CCLR bit to

zero ensures that a compare match with the CCRP values will reset the internal counter. As the

CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256

clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at

its maximum value.

Standard Type TM Operating Modes

The Standard Type TM can operate in one of five oper-

ating modes, Compare Match Output Mode, PWM Out-

put Mode, Single Pulse Output Mode, Capture Input

Mode or Timer/Counter Mode. The operating mode is

selected using the TnM1 and TnM0 bits in the TMnC1

Compare Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1

once the counter is enabled and running it can be

cleared by three methods. These are a counter over-

flow, a compare match from Comparator A and a com-

pare match from Comparator P. When the TnCCLR bit is

low, there are two ways in which the counter can be

cleared. One is when a compare match from Compara-

tor P, the other is when the CCRP bits are all zero which

allows the counter to overflow. Here both TnAF and

TnPF interrupt request flags for Comparator A and Com-

parator P respectively, will both be generated.

If the TnCCLR bit in the TMnC1 register is high then the

counter will be cleared when a compare match occurs

from Comparator A. However, here only the TnAF inter-

rupt request flag will be generated even if the value of

the CCRP bits is less than that of the CCRA registers.

Therefore when TnCCLR is high no TnPF interrupt re-

quest flag will be generated. In the Compare Match Out-

put Mode, the CCRA can not be set to

²0².

As the name of the mode suggests, after a comparison

is made, the TM output pin, will change state. The TM

output pin condition however only changes state when

an TnAF interrupt request flag is generated after a com-

pare match occurs from Comparator A. The TnPF inter-

rupt request flag, generated from a compare match

occurs from Comparator P, will have no effect on the TM

output pin. The way in which the TM output pin changes

state are determined by the condition of the TnIO1 and

TnIO0 bits in the TMnC1 register. The TM output pin can

be selected using the TnIO1 and TnIO0 bits to go high,

to go low or to toggle from its present condition when a

compare match occurs from Comparator A. The initial

condition of the TM output pin, which is setup after the

TnON bit changes from low to high, is setup using the

TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero

then no pin change will take place.

HT68FU50 数据表(PDF) 107 Page - Holtek Semiconductor Inc

HT68FU50 数据表(HTML) 107 Page - Holtek Semiconductor Inc

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