HT68FU50 datasheet(111/244 Pages) HOLTEK

111 / 244 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

111

March 15, 2011

Counter Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

Time

Counter cleared

by CCRP

Pause Resume

Counter Stop if

TnON bit low

Counter Reset when

TnON returns high

TnDPX = 0; TnM [1:0] = 10

PWM Duty Cycle

set by CCRA

PWM resumes

operation

Output controlled by

other pin-shared function

Output Inverts

when TnPOL = 1

PWM Period

set by CCRP

TM O/P Pin

(TnOC=0)

PWM Mode -- TnDPX = 0

Note:

1. Here TnDPX=0 -- Counter cleared by CCRP

2. A counter clear sets the PWM Period

3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01

4. The TnCCLR bit has no influence on PWM operation

· 16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=1

CCRP

1~255

Period

CCRA

Duty

CCRP

´ 256

65536

The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cy-

cle is defined by the (CCRP x 256) except when the CCRP value is equal to 0.

HT68FU50 数据表(PDF) 111 Page - Holtek Semiconductor Inc

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HT68FU50 数据表(PDF) 111 Page - Holtek Semiconductor Inc

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