HT68FU50 datasheet(114/244 Pages) HOLTEK

114 / 244 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

114

March 15, 2011

However a compare match from Comparator A will also

automatically clear the TnON bit and thus generate the

Single Pulse output trailing edge. In this way the CCRA

value can be used to control the pulse width. A compare

match from Comparator A will also generate a TM inter-

rupt. The counter can only be reset back to zero when

the TnON bit changes from low to high when the counter

restarts. In the Single Pulse Mode CCRP is not used.

The TnCCLR and TnDPX bits are not used in this Mode.

Capture Input Mode

To select this mode bits TnM1 and TnM0 in the TMnC1

ables external signals to capture and store the present

value of the internal counter and can therefore be used

for applications such as pulse width measurements.

The external signal is supplied on the TPn_0 or TPn_1

pin, whose active edge can be either a rising edge, a

falling edge or both rising and falling edges; the active

edge transition type is selected using the TnIO1 and

TnIO0 bits in the TMnC1 register. The counter is started

when the TnON bit changes from low to high which is ini-

tiated using the application program.

When the required edge transition appears on the

TPn_0 or TPn_1 pin the present value in the counter will

be latched into the CCRA registers and a TM interrupt

generated. Irrespective of what events occur on the

TPn_0 or TPn_1 pin the counter will continue to free run

until the TnON bit changes from high to low. When a

CCRP compare match occurs the counter will reset

back to zero; in this way the CCRP value can be used to

control the maximum counter value. When a CCRP

compare match occurs from Comparator P, a TM inter-

rupt will also be generated. Counting the number of

overflow interrupt signals from the CCRP can be a use-

ful method in measuring long pulse widths. The TnIO1

and TnIO0 bits can select the active trigger edge on the

TPn_0 or TPn_1 pin to be a rising edge, falling edge or

both edge types. If the TnIO1 and TnIO0 bits are both

set high, then no capture operation will take place irre-

spective of what happens on the TPn_0 or TPn_1 pin,

however it must be noted that the counter will continue

to run.

As the TPn_0 or TPn_1 pin is pin shared with other func-

tions, care must be taken if the TM is in the Input Cap-

ture Mode. This is because if the pin is setup as an

output, then any transitions on this pin may cause an in-

put capture operation to be executed. The TnCCLR and

TnDPX bits are not used in this Mode.

Counter Value

CCRP

TnON

TnPAU

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

CCRA

Value

Time

Counter cleared

by CCRP

Pause

Resume

Counter

Reset

TnM [1:0] = 01

TM capture

pin TPn_x

Counter

Stop

TnIO [1:0]

Value

Active

edge

Active

edge

Active edge

Rising edge

Falling edge

Both edges

Disable Capture

Capture Input Mode

Note:

1. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits

2. A TM Capture input pin active edge transfers the counter value to CCRA

3. TnCCLR bit not used

4. No output function -- TnOC and TnPOL bits are not used

5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to

zero.

HT68FU50 数据表(PDF) 114 Page - Holtek Semiconductor Inc

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