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HT68FU50 数据表(PDF) 112 Page - Holtek Semiconductor Inc |
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HT68FU50 数据表(HTML) 112 Page - Holtek Semiconductor Inc |
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112 / 244 page  HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Rev. 1.50 112 March 15, 2011 Counter Value CCRP CCRA TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) Time Counter cleared by CCRA Pause Resume Counter Stop if TnON bit low Counter Reset when TnON returns high TnDPX = 1; TnM [1:0] = 10 PWMDutyCycle set by CCRP PWM resumes operation Output controlled by other pin-shared function Output Inverts when TnPOL = 1 PWM Period set by CCRA TM O/P Pin (TnOC=0) PWM Mode -- TnDPX = 1 Note: 1. Here TnDPX=1 -- Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation |
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