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GS9062-CFE3 数据表(PDF) 6 Page - Gennum Corporation |
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GS9062-CFE3 数据表(HTML) 6 Page - Gennum Corporation |
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6 / 46 page ![]() GS9062 Data Sheet 22209 - 7 February 2007 6 of 46 1.2 Pin Descriptions Table 1-1: Pin Descriptions Pin Number Name Timing Type Description 1 CP_VDD – Power Power supply connection for the charge pump. Connect to +3.3V DC analog. 2 PD_GND – Power Ground connection for the phase detector. Connect to analog GND. 3 PD_VDD – Power Power supply connection for the phase detector. Connect to +1.8V DC analog. 4, 6 – 8, 10 – 11, 14 – 17, 31, 70 – 71 NC – – No connect. 5 RSV – – Reserved – connect to analog ground. 9 DVB_ASI Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. When set HIGH in conjunction with SMPTE_BYPASS = LOW, the device will be configured to operate in DVB-ASI mode. When set LOW, the device will not support the encoding of received DVB-ASI data. 12 20bit/10bit Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select the input data bus width in SMPTE or Data-Through modes. This signal is ignored in DVB-ASI mode. When set HIGH, the parallel input will be 20-bit demultiplexed data. When set LOW, the parallel input will be 10-bit multiplexed data. 13 IOPROC_EN/DIS Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable I/O processing features. When set HIGH, the following I/O processing features of the device are enabled: • EDH Packet Generation and Insertion • SMPTE 352M Packet Generation and Insertion • ANC Data Checksum Calculation and Insertion • TRS Generation and Insertion • Illegal Code Remapping To enable a subset of these features, keep IOPROC_EN/DIS HIGH and disable the individual feature(s) in the IOPROC_DISABLE register accessible via the host interface. When set LOW, the I/O processing features of the device are disabled, regardless of whether the features are enabled in the IOPROC_DISABLE register. |
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