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GS9062-CFE3 数据表(PDF) 1 Page - Gennum Corporation |
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GS9062-CFE3 数据表(HTML) 1 Page - Gennum Corporation |
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1 / 46 page  www.gennum.com GS9062 HD-LINX® II SD-SDI and DVB-ASI Serializer with ClockCleaner™ GS9062 Data Sheet 22209 - 7 February 2007 1 of 46 Key Features • SMPTE 259M-C compliant scrambling and NRZ → NRZI encoding (with bypass) • DVB-ASI sync word insertion and 8b/10b encoding • adjustable loop bandwidth • user selectable additional processing features including: • ANC data checksum, and line number calculation and insertion • TRS and EDH packet generation and insertion • illegal code remapping • internal flywheel for noise immune TRS generation • 20-bit / 10-bit CMOS parallel input data bus • 27MHz / 13.5MHz parallel digital input • automatic standards detection and indication • Pb-free and RoHS compliant • 1.8V core power supply and 3.3V charge pump power supply • 3.3V digital I/O supply • JTAG test interface • small footprint compatible with GS1560A, GS1561, GS1532, and GS9060 Applications • SMPTE 259M-C Serial Digital Interfaces • DVB-ASI Serial Digital Interfaces Description The GS9062 is a dual-standard serializer with an integrated cable driver. When used in conjunction with the GO1555/GO1525* Voltage Controlled Oscillator, a transmit solution can be realized for SD-SDI and DVB-ASI applications. The device features an internal PLL, which can be configured for loop bandwidth as narrow as 100kHz. Thus the GS9062 can tolerate in excess of 300ps jitter on the input PCLK and still provide output jitter well within SMPTE specification. Connect the output clocks from Gennum’s GS4911 clock generator directly to the GS9062’s PCLK input and configure the GS9062’s loop bandwidth accordingly. In addition to serializing the input, the GS9062 performs NRZ-to-NRZI encoding and scrambling as per SMPTE 259M-C when operating in SMPTE mode. When operating in DVB-ASI mode, the device will insert K28.5 sync characters and 8b/10b encode the data prior to serialization. Parallel data inputs are provided for 10-bit multiplexed or 20-bit demultiplexed formats. An appropriate parallel clock input signal is also required. The integrated cable driver features an output mute on loss of parallel clock, high impedance mode and adjustable signal swing. The GS9062 also includes a range of data processing functions including automatic standards detection and EDH support. The device can also insert TRS signals, re-map illegal code words and insert SMPTE 352M payload identifier packets. All processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming. The GS9062 is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS compliant). *For new designs use GO1555 |
类似零件编号 - GS9062-CFE3 |
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类似说明 - GS9062-CFE3 |
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