GS9062-CFE3 datasheet(14/46 Pages) GENNUM

14 / 46 page

GS9062 Data Sheet

22209 - 7

February 2007

14 of 46

Parallel Input

Parallel Clock Frequency

fPCLK

–

13.5

–

27.0

MHz

–

Parallel Clock Duty Cycle

DCPCLK

–40

–

Input Data Setup Time

tSU

–2

–

Input Data Hold Time

tIH

–1.5

–

Serial Digital Output

Serial Output Data Rate

DRSDO

–

270

–

Mb/s

–

Serial Output Swing

∆V

SDD

RSET = 281

Ω

Load = 75

Ω

–

800

–

mVp-p

–

Serial Output Rise Time

20% ~ 80%

trSDO

ORL compensation

using recommended

circuit

400

550

1500

–

Serial Output Fall Time

20% ~ 80%

tfSDO

ORL compensation

using recommended

circuit

400

550

1500

–

Serial Output Intrinsic Jitter

tIJ

Pseudorandom and

pathological signal

–

270

350

–

Serial Output Duty Cycle

Distortion

DCDSDO

––

–

GSPI

GSPI Input Clock Frequency

fSCLK

––

–

6.6

MHz

–

GSPI Input Clock Duty Cycle

DCSCLK

–40

6,7

–

GSPI Input Data Setup Time

–

6,7

–

GSPI Input Data Hold Time

–

1.43

–

6,7

–

GSPI Output Data Hold Time

–

2.10

–

6,7

–

GSPI Output Data Delay Time

–

7.27

6,7

–

TEST LEVELS

1. Production test at room temperature and nominal supply voltage with

guardbands for supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage with

guardbands for supply and temperature ranges using correlated test.

3. Production test at room temperature and nominal supply voltage.

4. QA sample test.

5. Calculated result based on Level 1, 2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization data of similar

product.

9. Indirect test.

NOTES

1. With 15pF load.

2. Serial Duty Cycle Distortion is defined here to be the

difference between the width of a ‘1’ bit, and the width of a

‘0’ bit.

3. See Device Power Up on page 41, Figure 3-13.

Table 2-2: AC Electrical Characteristics (Continued)

TA = 0°C to 70°C, unless otherwise shown

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Test

Levels

Notes

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