GS9062-CFE3 datasheet(39/46 Pages) GENNUM

39 / 46 page

GS9062 Data Sheet

22209 - 7

February 2007

39 of 46

3.10.2 Data Read and Write Timing

Read and write mode timing for the GSPI interface is shown in Figure 3-9 and

Figure 3-10 respectively. The maximum SCLK frequency allowed is 6.6MHz.

When writing to the registers via the GSPI, the MSB of the data word may be

presented to SDIN immediately following the falling edge of the LSB of the

command word. All SDIN data is sampled on the rising edge of SCLK.

When reading from the registers via the GSPI, the MSB of the data word will be

available on SDOUT 12ns (t

5 in Figure 3-9) following the falling edge of the LSB of

the command word, and thus may be read by the host on the very next rising edge

of the clock. The remaining bits are clocked out by the GS9062 on the negative

edges of SCLK.

Figure 3-9: GSPI Read Mode Timing

Figure 3-10: GSPI Write Mode Timing

3.10.3 Configuration and Status Registers

Table 3-11 summarizes the GS9062's internal status and configuration registers.

All of these registers are available to the host via the GSPI and are all individually

addressable.

Where status registers contain less than the full 16 bits of information however, two

or more registers may be combined at a single logical address.

SDOUT

R/W

RSV

D15

D14

D13

D12

D11

D10

SCLK

SDIN

RSV

input data

setup time

duty

cycle

period

output data

hold time

R/W

RSV

D15

D14

D13

D12

D11

D10

SCLK

SDIN

RSV

input data

setup time

duty

cycle

period

GS9062-CFE3 数据表(PDF) 39 Page - Gennum Corporation

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