GS9062-CFE3 datasheet(8/46 Pages) GENNUM

8 / 46 page

GS9062 Data Sheet

22209 - 7

February 2007

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CS_TMS

Synchronous

with

SCLK_TCK

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Chip Select / Test Mode Select

Host Mode (JTAG/HOST = LOW)

CS_TMS operates as the host interface chip select, CS, and is

active LOW.

JTAG Test Mode (JTAG/HOST = HIGH)

CS_TMS operates as the JTAG test mode select, TMS, and is

active HIGH.

NOTE: If the host interface is not being used, tie this pin HIGH.

SDOUT_TDO

Synchronous

with

SCLK_TCK

Output

CONTROL SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data Output / Test Data Output

Host Mode (JTAG/HOST = LOW)

SDOUT_TDO operates as the host interface serial output,

SDOUT, used to read status and configuration information from

the internal registers of the device.

JTAG Test Mode (JTAG/HOST = HIGH)

SDOUT_TDO operates as the JTAG test data output, TDO.

SDIN_TDI

Synchronous

with

SCLK_TCK

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data In / Test Data Input

Host Mode (JTAG/HOST = LOW)

SDIN_TDI operates as the host interface serial input, SDIN, used

to write address and configuration information to the internal

registers of the device.

JTAG Test Mode (JTAG/HOST = HIGH)

SDIN_TDI operates as the JTAG test data input, TDI.

NOTE: If the host interface is not being used, tie this pin HIGH.

SCLK_TCK

Non

Synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data Clock / Test Clock.

Host Mode (JTAG/HOST = LOW)

SCLK_TCK operates as the host interface burst clock, SCLK.

Command and data read/write words are clocked into the device

synchronously with this clock.

JTAG Test Mode (JTAG/HOST = HIGH)

SCLK_TCK operates as the JTAG test clock, TCK.

NOTE: If the host interface is not being used, tie this pin HIGH.

BLANK

Synchronous

with PCLK

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to enable or disable input data blanking.

When set LOW, the luma and chroma input data is set to the

appropriate blanking levels. Horizontal and vertical ancillary

spaces will also be set to blanking levels.

When set HIGH, the luma and chroma input data pass through

the device unaltered.

Table 1-1: Pin Descriptions (Continued)

Number

Name

Timing

Type

Description

GS9062-CFE3 数据表(PDF) 8 Page - Gennum Corporation

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GS9062-CFE3 数据表(PDF) 8 Page - Gennum Corporation

GS9062-CFE3 数据表(HTML) 8 Page - Gennum Corporation

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