AFS090 datasheet(30/334 Pages) MICROSEMI

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Device Architecture

2- 14

R e visio n 2

VersaNet Global Networks and Spine Access

The Fusion architecture contains a total of 18 segmented global networks that can access the

VersaTiles, SRAM, and I/O tiles on the Fusion device. There are 6 chip (main) global networks that

access the entire device and 12 quadrant networks (3 in each quadrant). Each device has a total of 18

globals. These VersaNet global networks offer fast, low-skew routing resources for high-fanout nets,

including clock signals. In addition, these highly segmented global networks offer users the flexibility to

create low-skew local networks using spines for up to 180 internal/external clocks (in an AFS1500

device) or other high-fanout nets in Fusion devices. Optimal usage of these low-skew networks can

result in significant improvement in design performance on Fusion devices.

The nine spines available in a vertical column reside in global networks with two separate regions of

scope: the quadrant global network, which has three spines, and the chip (main) global network, which

has six spines. Note that there are three quadrant spines in each quadrant of the device. There are four

quadrant global network regions per device (Figure 2-12 on page 2-13).

The spines are the vertical branches of the global network tree, shown in Figure 2-11 on page 2-12. Each

spine in a vertical column of a chip (main) global network is further divided into two equal-length spine

segments: one in the top and one in the bottom half of the die.

Each spine and its associated ribs cover a certain area of the Fusion device (the "scope" of the spine;

see Figure 2-11 on page 2-12). Each spine is accessed by the dedicated global network MUX tree

architecture, which defines how a particular spine is driven—either by the signal on the global network

from a CCC, for example, or another net defined by the user (Figure 2-13). Quadrant spines can be

driven from user I/Os on the north and south sides of the die, via analog I/Os configured as direct digital

inputs. The ability to drive spines in the quadrant global networks can have a significant effect on system

performance for high-fanout inputs to a design.

Details of the chip (main) global network spine-selection MUX are presented in Figure 2-13. The spine

drivers for each spine are located in the middle of the die.

Quadrant spines are driven from a north or south rib. Access to the top and bottom ribs is from the corner

CCC or from the I/Os on the north and south sides of the device. For details on using spines in Fusion

devices, see the application note Using Global Resources in Actel Fusion Devices.

Figure 2-13 • Spine-Selection MUX of Global Tree

Internal/External

Signal

Internal/External

Signal

Internal/External

Signals

Spine

Global Rib

Global Driver MUX

Tree Node MUX

Internal/External

Signals

Tree Node MUX

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