AFS090 datasheet(9/334 Pages) MICROSEMI

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Fusion Family of Mixed Signal FPGAs

R e visio n 2

1 -3

Live at Power-Up

Flash-based Fusion devices are Level 0 live at power-up (LAPU). LAPU Fusion devices greatly simplify

total system design and reduce total system cost by eliminating the need for CPLDs. The Fusion LAPU

clocking (PLLs) replaces off-chip clocking resources. The Fusion mix of LAPU clocking and analog

resources makes these devices an excellent choice for both system supervisor and system management

functions. LAPU from a single 3.3 V source enables Fusion devices to initiate, control, and monitor

multiple voltage supplies while also providing system clocks. In addition, glitches and brownouts in

system power will not corrupt the Fusion device flash configuration. Unlike SRAM-based FPGAs, the

device will not have to be reloaded when system power is restored. This enables reduction or complete

removal of expensive voltage monitor and brownout detection devices from the PCB design. Flash-

based Fusion devices simplify total system design and reduce cost and design risk, while increasing

system reliability.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. Another

source of radiation-induced firm errors is alpha particles. For an alpha to cause a soft or firm error, its

source must be in very close proximity to the affected circuit. The alpha source must be in the package

molding compound or in the die itself. While low-alpha molding compounds are being used increasingly,

this helps reduce but does not entirely eliminate alpha-induced firm errors.

Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not occur in Fusion flash-based FPGAs. Once it is programmed,

the flash cell configuration element of Fusion FPGAs cannot be altered by high-energy neutrons and is

therefore immune to errors from them.

Recoverable (or soft) errors occur in the user data SRAMs of all FPGA devices. These can easily be

mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based Fusion devices exhibit power characteristics similar to those of an ASIC, making them an

ideal choice for power-sensitive applications. With Fusion devices, there is no power-on current surge

and no high current transition, both of which occur on many FPGAs.

Fusion devices also have low dynamic power consumption and support both low power standby mode

and very low power sleep mode, offering further power savings.

Advanced Flash Technology

The Fusion family offers many benefits, including nonvolatility and reprogrammability through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows very high logic utilization (much

higher than competing SRAM technologies) without compromising device routability or performance.

Logic functions within the device are interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary Fusion architecture provides granularity comparable to standard-cell ASICs. The Fusion

device consists of several distinct and programmable architectural features, including the following

(Figure 1-1 on page 1-5):

•

Embedded memories

– Flash memory blocks

–FlashROM

– SRAM and FIFO

•

Clocking resources

– PLL and CCC

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