AFS090 datasheet(17/334 Pages) MICROSEMI

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R e visio n 2

2 -1

2 – Device Architecture

Fusion Stack Architecture

To manage the unprecedented level of integration in Fusion devices, Microsemi developed the Fusion

technology stack (Figure 2-1). This layered model offers a flexible design environment, enabling design

at very high and very low levels of abstraction. Fusion peripherals include hard analog IP and hard and

soft digital IP. Peripherals communicate across the FPGA fabric via a layer of soft gates—the Fusion

backbone. Much more than a common bus interface, this Fusion backbone integrates a micro-sequencer

within the FPGA fabric and configures the individual peripherals and supports low-level processing of

peripheral data. Fusion applets are application building blocks that can control and respond to

peripherals and other system signals. Applets can be rapidly combined to create large applications. The

technology is scalable across devices, families, design types, and user expertise, and supports a well-

defined interface for external IP and tool integration.

At the lowest level, Level 0, are Fusion peripherals. These are configurable functional blocks that can be

hardwired structures such as a PLL or analog input channel, or soft (FPGA gate) blocks such as a UART

or two-wire serial interface. The Fusion peripherals are configurable and support a standard interface to

facilitate communication and implementation.

Connecting and controlling access to the peripherals is the Fusion backbone, Level 1. The backbone is a

soft-gate structure, scalable to any number of peripherals. The backbone is a bus and much more; it

manages peripheral configuration to ensure proper operation. Leveraging the common peripheral

interface and a low-level state machine, the backbone efficiently offloads peripheral management from

the system design. The backbone can set and clear flags based upon peripheral behavior and can define

performance criteria. The flexibility of the stack enables a designer to configure the silicon, directly

bypassing the backbone if that level of control is desired.

One step up from the backbone is the Fusion applet, Level 2. The applet is an application building block

that implements a specific function in FPGA gates. It can react to stimuli and board-level events coming

through the backbone or from other sources, and responds to these stimuli by accessing and

manipulating peripherals via the backbone or initiating some other action. An applet controls or responds

to the peripheral(s). Applets can be easily imported or exported from the design environment. The applet

structure is open and well-defined, enabling users to import applets from Microsemi, system developers,

third parties, and user groups.

Note:

Levels 1, 2, and 3 are implemented in FPGA logic gates.

Figure 2-1 •

Fusion Architecture Stack

Flash

Memory

Analog

Smart

Peripheral 1

Analog

Smart

Peripheral 2

Analog

Smart

Peripheral n

Smart Peripherals

in FPGA

Fabric

(e.g., Logic, PLL, FIFO)

Fusion Smart Backbone

Fusion Applets

User Applications

Level 1

Level 0

Level 2

Level 3

Optional ARM or 8051 Processor

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