AFS090 datasheet(80/334 Pages) MICROSEMI

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Device Architecture

2- 64

R e visio n 2

RAM512X18 exhibits slightly different behavior from RAM4K9, as it has dedicated read and write ports.

WW and RW

These signals enable the RAM to be configured in one of the two allowable aspect ratios (Table 2-30).

WD and RD

These are the input and output data signals, and they are 18 bits wide. When a 512×9 aspect ratio is

used for write, WD[17:9] are unused and must be grounded. If this aspect ratio is used for read, then

RD[17:9] are undefined.

WADDR and RADDR

These are read and write addresses, and they are nine bits wide. When the 256×18 aspect ratio is used

for write or read, WADDR[8] or RADDR[8] are unused and must be grounded.

WCLK and RCLK

These signals are the write and read clocks, respectively. They are both active high.

WEN and REN

These signals are the write and read enables, respectively. They are both active low by default. These

signals can be configured as active high.

RESET

This active low signal resets the output to zero, disables reads and/or writes from the SRAM block, and

clears the data hold registers when asserted. It does not reset the contents of the memory.

PIPE

This signal is used to specify pipelined read on the output. A Low on PIPE indicates a nonpipelined read,

and the data appears on the output in the same clock cycle. A High indicates a pipelined read, and data

appears on the output in the next clock cycle.

Clocking

The dual-port SRAM blocks are only clocked on the rising edge. SmartGen allows falling-edge-triggered

clocks by adding inverters to the netlist, hence achieving dual-port SRAM blocks that are clocked on

either edge (rising or falling). For dual-port SRAM, each port can be clocked on either edge or by

separate clocks, by port.

Fusion devices support inversion (bubble pushing) throughout the FPGA architecture, including the clock

input to the SRAM modules. Inversions added to the SRAM clock pin on the design schematic or in the

HDL code will be automatically accounted for during design compile without incurring additional delay in

the clock path.

The two-port SRAM can be clocked on the rising edge or falling edge of WCLK and RCLK.

If negative-edge RAM and FIFO clocking is selected for memory macros, clock edge inversion

management (bubble pushing) is automatically used within the Fusion development tools, without

performance penalty.

Table 2-30 • Aspect Ratio Settings for WW[1:0]

WW[1:0]

RW[1:0]

D×W

512×9

256×18

00, 11

Reserved

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