AFS090 datasheet(122/334 Pages) MICROSEMI

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Device Architecture

2- 10 6

R e v isio n 2

TUE – Total Unadjusted Error

TUE is a comprehensive specification that includes linearity errors, gain error, and offset error. It is the

worst-case deviation from the ideal device performance. TUE is a static specification (Figure 2-85).

ADC Operation

Once the ADC has powered up and been released from reset, ADCRESET, the ADC will initiate a

calibration routine designed to provide optimal ADC performance. The Fusion ADC offers a robust

calibration scheme to reduce integrated offset and linearity errors. The offset and linearity errors of the

main capacitor array are compensated for with an 8-bit calibration capacitor array. The offset/linearity

error calibration is carried out in two ways. First, a power-up calibration is carried out when the ADC

comes out of reset. This is initiated by the CALIBRATE output of the Analog Block macro and is a fixed

number of ADC_CLK cycles (3,840 cycles), as shown in Figure 2-87 on page 2-113. In this mode, the

linearity and offset errors of the capacitors are calibrated.

To further compensate for drift and temperature-dependent effects, every conversion is followed by post-

calibration of either the offset or a bit of the main capacitor array. The post-calibration ensures that, over

time and with temperature, the ADC remains consistent.

After both calibration and the setting of the appropriate configurations, as explained above, the ADC is

ready for operation. Setting the ADCSTART signal high for one clock period will initiate the sample and

conversion of the analog signal on the channel as configured by CHNUMBER[4:0]. The status signals

SAMPLE and BUSY will show when the ADC is sampling and converting (Figure 2-89 on page 2-114).

Both SAMPLE and BUSY will initially go high. After the ADC has sampled and held the analog signal,

SAMPLE will go low. After the entire operation has completed and the analog signal is converted, BUSY

will go low and DATAVALID will go high. This indicates that the digital result is available on the

RESULT[11:0] pins.

DATAVALID will remain high until a subsequent ADC_START is issued. The DATAVALID goes low on the

rising edge of SYSCLK as shown in Figure 2-88 on page 2-113. The RESULT signals will be kept

constant until the ADC finishes the subsequent sample. The next sampled RESULT will be available

when DATAVALID goes high again. It is ideal to read the RESULT when DATAVALID is '1'. The RESULT

is latched and remains unchanged until the next DATAVLAID rising edge.

Figure 2-85 • Total Unadjusted Error (TUE)

Input Voltage to Prescaler

IDEAL OUTPUT

TUE = ±0.5 LSB

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