AFS090 datasheet(184/334 Pages) MICROSEMI

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Device Architecture

2- 16 8

R e v isio n 2

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-90 • Summary of AC Measuring Points

Applicable to All I/O Bank Types

Standard

Input Reference Voltage

(VREF_TYP)

Board Termination Voltage

(VTT_REF)

Measuring Trip Point

(Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS

–

1.4 V

2.5 V LVCMOS

–

1.2 V

1.8 V LVCMOS

–

0.90 V

1.5 V LVCMOS

–

0.75 V

3.3 V PCI

–

0.285 * VCCI (RR)

0.615 * VCCI (FF))

3.3 V PCI-X

–

0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V GTL

0.8 V

1.2 V

VREF

2.5 V GTL

0.8 V

1.2 V

VREF

3.3 V GTL+

1.0 V

1.5 V

VREF

2.5 V GTL+

1.0 V

1.5 V

VREF

HSTL (I)

0.75 V

VREF

HSTL (II)

0.75 V

VREF

SSTL2 (I)

1.25 V

VREF

SSTL2 (II)

1.25 V

VREF

SSTL3 (I)

1.5 V

1.485 V

VREF

SSTL3 (II)

1.5 V

1.485 V

VREF

LVDS

–

Cross point

LVPECL

–

Cross point

Table 2-91 • I/O AC Parameter Definitions

Parameter

Definition

tDP

Data to Pad delay through the Output Buffer

tPY

Pad to Data delay through the Input Buffer with Schmitt trigger disabled

tDOUT

Data to Output Buffer delay through the I/O interface

tEOUT

Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN

Input Buffer to Data delay through the I/O interface

tPYS

Pad to Data delay through the Input Buffer with Schmitt trigger enabled

tHZ

Enable to Pad delay through the Output Buffer—High to Z

tZH

Enable to Pad delay through the Output Buffer—Z to High

tLZ

Enable to Pad delay through the Output Buffer—Low to Z

tZL

Enable to Pad delay through the Output Buffer—Z to Low

tZHS

Enable to Pad delay through the Output Buffer with delayed enable—Z to High

tZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

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