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AS1160 数据表(PDF) 13 Page - ams AG |
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AS1160 数据表(HTML) 13 Page - ams AG |
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13 / 29 page  www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1.01 13 - 29 AS1160/AS1161 Datasheet - Ti m i n g D i a g r a m s Figure 18. Serializer Bus LVDS Output Load and Transition Times Figure 19. Deserializer CMOS/TTL Output Load and Transition Times Figure 20. Serializer Input Clock Transition Time Figure 21. Serializer Setup and Hold Times tLLHT tLHLT VDIFF 20% 80% 20% 80% VDIFF = 0V RLOAD DO+ DO- 10pF 10pF VDIFF = DO+ - DO- 28 Ω tCLH 20% 80% 20% 80% Deserializer 15pF CMOS/TTL Output tCHL tCLKT TCLK 10% 90% 10% 90% 3V 0V tCLKT 1.5V 1.5V 1.5V tTCP tDIS tDIH 1.5V Setup 1.5V Hold TCLK DIN0:9 Timing shown for TCKR/FN is low |
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