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AS1160 数据表(PDF) 17 Page - ams AG

部件名 AS1160
功能描述  20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer
PDF  29 Pages
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制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

AS1160 数据表(HTML) 17 Page - ams AG

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www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61
Revision 1.01
17 - 29
AS1160/AS1161
Datasheet - Ti m i n g D i a g r a m s
Figure 30. Deserializer PLL Lock Times and PWDNN Tri-State Delays
Figure 31. Deserializer PLL Lock Time from SYNCPAT
2.0V
Data
PWDNN
REFCLK
RI+
RI-
tDSR1
0.8V
Don’t Care
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
SYNCPATs
LOCKN
ROUT0:9
RCLK
REN
tZHLK
tZHR or tZLR
tHZR or tLZR
SYNC Symbol or DIN0:9
RCKR/FN = low
tRCLKL
REN
Tri-State
Tri-State
RCLK
Tri-State
Tri-State
ROUT0:9
SYNC Symbol or DIN0:9
tZHR or tZLR
tHZR or tLZR
Tri-State
LOCKN
REFCLK
RI+
RI-
PWDNN
Data
SYNCPATs
tDSR2
0.8V
1.3V
1.1V
Don’t Care
1.2V
tRCLKL



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