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AS1160 数据表(PDF) 16 Page - ams AG |
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AS1160 数据表(HTML) 16 Page - ams AG |
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16 / 29 page  www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1.01 16 - 29 AS1160/AS1161 Datasheet - Ti m i n g D i a g r a m s Figure 27. Deserializer Delay Figure 28. Deserializer Data Valid Out Times Figure 29. Deserializer Tri-State Test Circuit and Timing Diagram Start Bit Stop Bit Start Bit DIN0:9 Symbol n + 1 DIN0:9 Symbol n DIN0:9 Symbol n + 1 tDD 1.3V 1.1V RCLK ROUT ROUT0:9 Symbol n - 1 ROUT0:9 Symbol ROUT0:9 Symbol n + 1 Start Bit Stop Bit Stop Bit R- R+ 1.5V 1.5V tHIGH tLOW tHIGH tLOW tROH tROS Data valid before RCLK RCLK RCKR/FN = Low RCLK RCKR/FN = High ROUT0:9 Data valid after RCLK 50Ω 500Ω 450Ω +7V LZ, ZL Open HZ, ZH OScope tZLR tLZR tZHR tHZR VOL VOH VOL VOH VOL + 0.5V VOH - 0.5V VOH - 0.5V VOL + 0.5V 1.5V 1.5V REN |
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