www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

Revision 1.01

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AS1160/AS1161

Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Figure 36. Typical Application

Noise Margin

The deserializer (AS1161) noise margin is the amount of input jitter (phase noise) that the deserializer can tolerate and

still reliably receive data. Various environmental and systematic factors include:

- Media: ISI (Inter Symbolic Interference), Large VCM shifts

Lock Loss Recovery

In the case where the deserializer (AS1161) loses lock during data transmission, up to 3 cycles of data that were previ-

ously received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that

invalid clock information be received 4 times in a row to indicate loss of lock. Since clock information has been lost, it is

possible that data was also lost during these cycles. Therefore, after the deserializer re-locks to the incoming data

stream and the deserializer LOCKN pin goes low, at least three previous data cycles should be suspect for bit errors.

The deserializer can re-lock to the incoming data stream by making the serializer re-send SYNCPATs.

Hot Insertion

As all BLVDS devices the AS1161 is hot pluggable but you have to follow some rules.

Hot insertion should be performed with pins making contact in the following order:

- Ground pins

- I/O pins

Note: When removing the device, the pin groups should be removed in reverse order from insertion.

AS1160

DO+

DO-

TCLK

TCKR/FN

Input

Latch

PLL

DIN0:9

Parallel

-to-

Serial

10

Timing &

Control

DEN

SYNC1

SYNC2

AS1161

RI+

RI-

Output

Latch

PLL

ROUT0:9

10

Timing &

Control

REFCLK

REN

LOCKN

RCLK

RCKR/

Parallel

-to-

Serial

JTAG

JTAG

56

Ω

PWDNN

PWDNN

ASIC/

FPGA/

DSP

ASIC/

FPGA/

DSP

VDD

VDD

Clock

Recovery