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Revision 1.01

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AS1160/AS1161

Datasheet - D e t a i l e d D e s c r i p t i o n

Data Transfer

After initialization, the serializer will accept data from inputs DIN0:DIN9. The serializer uses TCLK to latch incoming

data. TCKR/FN selects which edge the serializer uses to strobe incoming data. TCKR/FN high selects the rising edge

for clocking data and low selects the falling edge. If SYNC1 or SYNC2 is high for more than 5 TCLK cycles, the data at

DIN0:DIN9 is ignored regardless of clock edge.

After determining which clock edge to use a start and stop bit, appended internally, frame the data bits in the register.

The start bit is always high and the stop bit is always low. In the serial stream the start and stop bits are used as the

embedded clock bits.

The serializer transmits serialized data and clock bits (10 + 2 bits) from the serial data output (DO+ and DO-) at 12

times the TCLK frequency. For example, if TCLK is 66MHz, the serial rate is 66 x 12 = 792 mega bits per second.

Since only 10 bits are from input data, the serial payload rate is 10 times the TCLK frequency (if TCLK = 66MHz, the

payload data rate is 66 x 10 = 660Mbps). The data source provides TCLK and must be in the range of 20MHz to

66MHz nominal.

The serializer outputs (DO+ and DO-) can drive a point-to-point connection (see Figure 37 on page 24) or a multidrop

configuration (see Figure 35). In a multidrop configuration one serializer is connected through a backplane bus with

limited multiple deserializers.

The outputs transmit data when DEN, PWDNN are high and SYNC1, SYNC2 are low.

Note: When DEN is driven low, the serializer output pins will enter tri-state.

Figure 35. Multidrop Configuration

When the deserializer synchronizes to the serializer, pin LOCKN is low. The deserializer locks to the internal clock and

input gates (15pF load) with a 66MHz clock.

ASIC

ASIC

ASIC

ASIC

ASIC

56

Ω

56

Ω

10-bit

10-bit

10-bit

10-bit

10-bit

Transmitter