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AS1160 数据表(PDF) 14 Page - ams AG

部件名 AS1160
功能描述  20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer
PDF  29 Pages
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制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

AS1160 数据表(HTML) 14 Page - ams AG

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www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61
Revision 1.01
14 - 29
AS1160/AS1161
Datasheet - Ti m i n g D i a g r a m s
Figure 22. Serializer Tri-State Test Circuit and Timing
Figure 23. Serializer Power Up Timing
Figure 24. Serializer PLL Lock Time and PWDNN Tri-State Delays
tZHD
tZLD
tLZD
tHZD
1.5V
1.5V
50%
50%
DO+
VOL
VOH
50%
50%
DEN
3V
0V
DEN
RLOAD
DO+
DO-
10pF
10pF
28
Ω
DO-
VDD
PWDNN
tPWDL
2.0V
0.8V
tHZD or tLZD
tZHD or tZLD
<400 Cycles
tPLD
DO+
DO-
PWDNN
TCLK
Tri-State
Tri-State
Output
Active
. . .
. . .



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