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AS1160 数据表(PDF) 18 Page - ams AG |
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AS1160 数据表(HTML) 18 Page - ams AG |
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18 / 29 page  www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1.01 18 - 29 AS1160/AS1161 Datasheet - Ti m i n g D i a g r a m s Figure 32. Definition of Deterministic Jitter (tDJIT) Figure 33. Receiver Bus LVDS Input Skew Margin Where: tSW is the setup and hold time (internal data sampling window). tDJIT is the serializer output bit position jitter as a result of jitter on TCLK. tRNM is the receiver noise time margin. Figure 34. Data Transfer Mode, VOD Diagram (VOD = DO+ - DO-) tDJIT(p-p) 0 Differential (DO+) - (DO-) Waveform Superimposed ICC Pattern Trigger tRNM 1.2V RI- RI+ VTH VTL 1.0V tSW Ideal Sampling Position tDJIT tRNM tDJIT AS1160 TCLK DIN0:9 DO- DO+ RLOAD Parallel to Serial 10 |
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