XTNETA1622DW datasheet(22/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

segmentation overview (continued)

The second method for transmitting a transparent-AAL packet differs from the first method only in that the PTI

bits in the last cell of the packet are not modified. The PTI bits are transmitted as they occur in the descriptor

entry for all cells in the packet. This method can be used to transmit VC-level OAM cells, which are single cell

packets that set the PTI bits to a value of l0x.

After segmenting the contents of a buffer, the current-data-byte count for the DMA entry is set to zero. The OWN

bit of the next entry of the completion ring selected for the channel is examined. If the entry is owned by the host,

the transmit-freeze bit in the status register is set and an interrupt is generated. Otherwise, a pointer to the start

of the buffer is placed in the entry.

The size of the internal transmit FIFO is four cells. The UTOPIA interface for the segmentation unit can operate

asynchronous to the PCI bus as cells are read from the transmit buffer in 8-bit bytes. The HEC byte for the ATM

header is calculated byte wise and inserted in the fifth-header octet as a cell is read. When the HEC error bit

in the configuration register is set, the HEC byte is inverted prior to being inserted into the outgoing byte stream

for test purposes. The segmentation UTOPIA bus implements parity generation.

reassembly overview

For reassembly operation, the host must allocate memory for the following memory data structures: data buffers

with descriptor entries, completion ring with/without interrupt pointers, the receive-free buffer rings/receive-free

buffer FIFO, the RX VPI/VCI DMA pointer table, and a DMA state table entry for each VCI. The TNETA1570

registers, which need to be initialized by the host for reassembly, are the configuration register, the

interrupt-mask register, the reassembly-global-timer register, the RX DMA-state-table register, the completion

ring with/without interrupt-size register, and the FIFO free-buffer-size register.

Free buffers are fetched using either the receive free-buffer ring or the receive free-buffer FIFO. If the free-buffer

rings are used, the lower eight bits of word 6 of the DMA state table entry are read to obtain the index for the

free-buffer rings. The index points to one of the 256 entries in the free-buffer-ring-pointer table. Each entry

contains the base address of each free-buffer ring, as well as the buffer size, the ring size, and the current index.

If the free-buffer FIFO is used, a read on the address in word 6 of the DMA state table provides the starting

address of a free buffer.

If the receive free-buffer-ring method is used, the host sets the OWN bit of a completion-ring entry to indicate

that the buffer is available for use by the TNETA1570. If no free buffers are available, buffer starvation occurs

and the reassembly of the packet is terminated.

The completion ring with/without interrupt is initialized by the host in the DMA state table entry. If a completion

ring with interrupt entry is posted and the TNETA 1570 interrupt-mask register allows, an interrupt is generated

on the PCI bus and an interrupt indication is placed in the status register. A bit in the configuration register can

be set so that an interrupt is posted at the completion of the segmentation of either a packet or a buffer.

The VPI of an incoming cell is used as an index into the VPI/VCI DMA pointer-table entry, which resides in control

memory. The information in the VPI/VCI DMA pointer table is used to determine if the VPI is enabled to receive

packets and if the VCI is within the valid range for the corresponding VPI. The index value in the VPI/VCI pointer

table together with the VCI value of the ATM cell are used to form the address of the DMA state-table entry for

that particular VCI. If a VCI is found to be out of range, an interrupt is generated.

If the PTI value of the incoming cell is 100, the cell is an OAM F5-segment cell. If the PTI value of the incoming

cell is 101, the cell is an OAM F5 end-to-end cell. Both OAM cells are routed to DMA channel 0. If the PTI value

is 110 or 111, the cell is routed to DMA channel 1. If the VCI value of the incoming cell is three, the cell is an

OAM F4 segment cell. If the VCI value of the incoming cell is four, the cell is an OAM F4 end-to-end cell and

both F4 OAM cells are routed to channel 2.

XTNETA1622DW 数据表(PDF) 22 Page - Texas Instruments

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