XTNETA1622DW datasheet(45/68 Pages) TI1

45 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

receive OAM-cell handling

The receive operation handles VP- and VC-level OAM cells. VC level OAM cells, which have a PTI value of 100,

101, 110, or 111, are routed to either receive DMA channel 0 or 1. VP-level OAM cells, which have a VCI value

of 3 or 4, are routed to receive DMA channel 2. These channels must be configured by software to handle a

counter-based transparent-AAL packet with a packet length of one cell. The assignment of the VP- and VC-level

OAM cells is shown below:

OAM CELL

RX DMA CHANNEL ASSIGNMENT

VC level with PTI = 10x

Channel 0

VC level with PTI = 11x

Channel 1

VP level with VCI = 3 or 4

Channel 2

In addition, the RX VPI/VCI DMA pointer table must not assign receive DMA channels 0 −2 for use in

reassembling incoming packets. OAM cells do not cause the RX unknown register and unknown-protocol

counter to be updated unless the VPI is not enabled or the RX DMA state table has the ON bit = 0 and

filter = 0. F4 OAMs (VP termination) are identified by VCI 3,4. As long as the VPI is enabled, the range is ignored

when identifying VCI 3,4 (the cells are always accepted). F5 OAMs (VC termination) are identified by

PTI = 4 or 5. As long as the VPI is enabled, the cells are accepted regardless of the VCI range. The ON bits

of the three dedicated OAM DMA channels should always be = 1. However, the TNETA1570 does not prohibit

the user from setting the ON bit = 0 to disable OAM reception.

reassembly-aging timer

The TNETA1570 provides a reassembly-aging-timer (RAT) mechanism for determining the time elapsed since

the start of AAL5 and PTI-based transparent packets and terminating their reassembly based on time-out values

programmed per VC.

control structures

The RAT function is enabled globally by the EN_RAT bit in the device-configuration register. The

reassembly-global-timer register (16 bits) and RAT-cycle-count register (15 bits) provide global control of this

function. The RAT control functions on a per-VC basis are the time-out value (12 bits) and the time-out count

(12 bits) in word 7 of the receive DMA state table entries.

There are four internal counters used for the RAT:

D The global-RAT timer. It decrements from the reassembly-global-timer-register value every PCI-clock

cycle. When it reaches zero, a global time-out is declared. A global time-out is an opportunity to age a single

VC.

D The RAT-cycle-count timer. It decrements from the RAT-cycle-count-register-value every global time-out.

When it reaches zero, the reassembly-aging timer is reset and a new global-timer cycle is started.

D The VCI increments. It starts at zero when the RAT-cycle-count timer is reset and increments every global

time-out until it reaches the max valid VCI value for the current VPI value.

D VPI increments. It starts at zero when the RAT-cycle-count timer is reset and increments every time the VCI

incrementer reaches the max VCI value for the VPI, or if the VPI value points to a VPI that is not enabled.

global timer

An internal global counter decrements its count starting at the reassembly-global-timer-register value on each

PCI-bus clock when the EN_RAT bit in the configuration register is set. For a 33-MHz PCI-bus clock, the 16-bit

counter counts to zero in 1.966 ms or less, depending on the reassembly-global-timer-register value. When the

timer reaches zero, a global time-out is declared.

XTNETA1622DW 数据表(PDF) 45 Page - Texas Instruments

XTNETA1622DW 数据表(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载