XTNETA1622DW datasheet(51/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

configuration space definition (continued)

ADDRESS

BYTE 3

BYTE 2

BYTE 1

BYTE 0

READ/WRITE

0x00

Device ID

Vendor ID

0x04

Status

Command

R/W

0x08

Class code

Revision ID

0x0C

BIST

Header type

Latency timer

Cache-line size†

R/W

0x10

Base address 0

R/W

0x14

Base address 1†

R/W

0x18

Base address 2†

R/W

0x1C

Base address 3†

R/W

0x20

Base address 4†

R/W

0x24

Base address 5†

R/W

0x28

Reserved (returns 0 when read)

—

0x2C

Reserved (returns 0 when read)

—

0x30

Expansion-ROM base address

R/W

0x34

Reserved (returns 0 when read)

—

0x38

Reserved (returns 0 when read)

—

0x3C

Maximum latency

Minimum grant

Interrupt pin

Interrupt line

R/W

0x40

Reserved

R/W

0x44 − 0xFF

Reserved (returns 0 when read)

† Optional registers not implemented that return 0 when read

device-identification registers

The system software identifies installed PCI peripherals using the vendor-ID, device-ID, revision-ID, and

class-code registers. The registers used for device identification are described below.

DESCRIPTION

HARDWIRED

VALUE

Vendor lD

Uniquely identifies the manufacturer of the device. Vendor ID is specified by the PCI-special-interest

group to ensure uniqueness.

104Ch

Device ID

Identifies a specific device from the manufacturer. The device ID is specified by the manufacturer.

A001h

Revision ID

Identifies a revision of the specific device. The revision ID is specified by the manufacturer.

00h

Class code

Identifies the generic function of the device

02h

Sub-class code

80h

Header type

Identifies the layout of bytes 10h through 3F and whether the device is single or multifunction

00h

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