XTNETA1622DW datasheet(28/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

transmit DMA state table (continued)

ENTRY

DESCRIPTION

Word 0

Control field, buffer offset, buffer data-byte count

Word 0

Word 1

Control field, buffer offset, buffer data-byte count

Current-buffer address

Word 1

Word 2

Current-buffer address

4-byte ATM header

Word 2

Word 3

4-byte ATM header

DMA state on/off

Word 3

Word 4

DMA state on/off

Next-buffer address

Word 4

Word 5

Next-buffer address

Start-of-buffer address

Word 5

Word 6

Word 7

Start-of-buffer address

Partial AAL5-transmit CRC

AAL5-control field and length field

Word 6

Word 7

Partial AAL5-transmit CRC

AAL5-control field and length field

word 0

Control (bits 31 − 25)

Reserved (bit 24)

Buffer Offset (bits 23 − 16)

Buffer Data-Byte Count (bits 15 − 0)

The contents of word 0 are copied directly from word 0 of the descriptor entry located at the start of each data

buffer.

act (ACTive) (bit 31)

This bit is set when the DMA channel is in the process of segmenting and transmitting a packet. This bit is cleared

by the TNETA1570 after the entire packet is transmitted.

start of packet (SOP) (bit 30)

This bit is set by the host indicating that this is the first buffer of a packet that consists of one or more buffers.

This bit is also set if a packet consists of only a single buffer. This bit is not checked by the TNETA1570.

end of packet (EOP) (bit 29)

This bit indicates that this is the last buffer of a packet; therefore, every packet has at least one buffer with the

EOP bit set. For a packet that consists of a single buffer, both the SOP and EOP bits are set.

abort (bit 28)

This bit indicates that EOP processing is initiated immediately and no further processing of the current packet

will occur. When both this bit and the AAL5-indicator bit are set, the AAL5 length field in the outgoing AAL5

packet is reset to zero.

transmit AAL-packet-type indicator (bits 27 and 26)

These bits are set by the host to indicate the AAL type of the packet being transmitted. Three options are

available for processing a packet for transmission as shown in the following table:

BIT 27

BIT 26

INDICATION

Transparent-AAL packet with PTI bits set to indicate EOP

AAL5

Transparent-AAL packet without PTI bits set to indicate EOP

Invalid

AAL5 processing includes the calculation of the 32-bit CRC and the addition of the pad, control, and length fields.

All buffers associated with an AAL5 packet must have the AAL5-indication bits set. When either of the other two

processing methods is chosen, the TNETA1570 does not perform packet-level processing, except for adding

the necessary pad to complete a 48-byte payload. If both bits 27 and 26 are set to zero, the device also sets

the PTI field in the last cell of a packet to a value of 0

× I to indicate EOP. If bits 27 and 26 are set to a value of

10, the PTI field in the last cell of the packet is not modified. This last method can be used to send VC-level OAM

cells, which require that the PTI value of the cell being transmitted be set to a value of 10x. The TNETA1570

does not modify the PTI field for these cells.

XTNETA1622DW 数据表(PDF) 28 Page - Texas Instruments

XTNETA1622DW 数据表(HTML) 28 Page - Texas Instruments

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