XTNETA1622DW datasheet(64/68 Pages) TI1

64 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

RX completion ring with interrupt (WI)-size register (continued)

The value in the registers is compared to an internal pointer counter that gets incremented when a

completion-ring entry is processed. When the value of the pointer counter equals the value in the register, the

pointer value is reset and the next pointer value is zero.

TX packet-segmentation ring-size register

Reserved (bits 15−8)

TX Packet-Segmentation-Ring Size (bits 7− 0)

This register contains the size of the TX packet-segmentation ring. The maximum size of this ring is 256 entries.

The size is restricted to a power of 2, i.e., 2, 4, 8, 16, 32, 64, 128, etc. This field is coded (ring size −1) to account

for entry 0; therefore, for a ring with 16 entries, the value of 0000 1111 is entered in this field. This is a 16-bit

FIFO free-buffer-size register

FIFO Free-Buffer Size (bits 15 − 0)

This register contains the size of the buffers used with the FIFO free-buffer structure. The size of the free buffer

is given in the number of ATM cells that the buffer can hold. If an AAL5 packet is to be placed in a single buffer,

the buffer must be able to hold 1366 cells. To program a buffer size of 64K byte, the value in the register should

be 64K / 48 rounded up = 1366(dec), (65536/48 = 1 365.3 = > 1366). This is a 16-bit register, read/write, and

is cleared when a hardware or software reset occurs.

VCI-mask register

VCI Mask (bits 15 − 0)

The 16-bit VCI mask field is uniformly imposed on all received cells, except OAM cells. If the bit value in the

mask = 1, the VCI bit in the incoming ATM cell is replaced by 0 before it is processed. If the bit value in the

mask = 0, the VCI bit is not affected.

The VCI mask works as follows:

D Cell arrives

D The cell is checked if it is a OAM cell; if so, it is processed as an OAM cell.

D VCI has mask imposed on it (invert and perform logical AND function with the bits in the register).This results

in a new 16-bit value.

D This new 16-bit value is compared to the valid VCI range value in the RX VPI/VCI pointer table to check

if it is out of range.

D If not out of range, the new 16-bit value is used to get to the appropriate RX DMA state-table entry.

The RAT timer is not affected. It uses the value programmed in the VPI/VCI DMA pointer table.

The received VPI/VCI appears in the RX completion ring and the RX data-buffer descriptor.

FIFO maximum occupancy value

Reserved (bits 15 − 12)

TX FIFO maximum

occupancy value

(bits 11 − 8)

Reserved (bits 7 − 5)

RX FIFO maximum

occupancy value

(bits 4 − 0)

XTNETA1622DW 数据表(PDF) 64 Page - Texas Instruments

XTNETA1622DW 数据表(HTML) 64 Page - Texas Instruments

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