XTNETA1622DW datasheet(25/68 Pages) TI1

25 / 68 page

TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

a receive DMA channel uses the receive completion ring with or without interrupt. The difference between the

two rings is that when an entry is posted to the completion ring with interrupt, an interrupt is generated by the

TNETA1570. When an entry is posted to the completion ring without interrupt, an interrupt is not generated. An

entry to either ring is posted when the reassembly process is completed. The sizes of the receive completion

rings are variable and are set by the host at initialization by writing to the receive completion ring with/without

interrupt size registers located inside the TNETA1570.

The TNETA1570 allows the use of multiple buffers to store an incoming packet (receive-buffer chaining). When

a new packet arrives or a buffer used to store cells from an incoming packet is filled, the device obtains an empty

buffer from either the receive free-buffer ring or the free-buffer FIFO, depending upon the configuration of the

receive DMA channel that is reassembling the packet. The device allows up to 256 different receive free-buffer

rings to be set up in host memory. If the user chooses to use free-buffer FIFOs, a separate receive free-buffer

FIFO can be assigned to each receive DMA channel.

The receive data structures that reside in control memory are the receive DMA state table, the receive VPI/VCI

DMA pointer table, and the receive free-buffer ring-pointer table. The receive DMA state table contains the state

information associated with the reassembly of an incoming packet. This table contains a maximum of 30 720

entries. The receive VPI/VCI DMA pointer table provides the address to the receive DMA state table entry for

a particular receive channel. The free-buffer ring-pointer block contains the addressing for the receive

free-buffer rings, as well as the size of the buffers associated with each free-buffer ring.

Internal registers are used for the maximum RX DMA state-table size, RX unknown, RX FIFO free-buffer size,

RX completion-ring pointers, RX completion-ring size, and reassembly-global timer.

HOST MEMORY

Data buffers with descriptor entries

RX completion ring with interrupt

RX completion ring without interrupt

RX free-buffer rings/receive free-buffer FIFOs

CONTROL MEMORY

RX DMA state table

RX VPI/VCI DMA pointer table

RX free-buffer ring pointers

RX VPI/VCI DMA pointer table

RX free-buffer ring pointers

internal registers

The TNETA1570 has several internal registers and counters for keeping statistics on selected parameters,

configuring the operation of the device, device status and interrupt masking, and for aging packets currently

undergoing reassembly. These registers are accessible by the host.

The internal registers and counters with some of their features are shown in the following table. A detailed

description can be found in the internal registers and counters section.

XTNETA1622DW 数据表(PDF) 25 Page - Texas Instruments

XTNETA1622DW 数据表(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载